📄 input.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity input is
port(keyIn:in std_logic;
clk:in std_logic;
keyOut:out std_logic);
end input;
architecture main of input is
signal a,b,c,d:std_logic;
begin
a<=(not keyIn) nand b;
b<=a nand (not c);
keyOut<=c and (not d);
process(clk)
begin
if(falling_edge(clk)) then
c<=a;
d<=c;
end if;
end process;
end main;
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