📄 piano.rpt
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3: "&__A__11/&__A__11_D2"
14: "&__A__5/&__A__5_D2"
25: "U31/countnum<3>"
4: "&__A__12/&__A__12_D2"
15: "&__A__6/&__A__6_D2"
26: "U31/syn4535/U31/syn4535_D2"
5: "&__A__13/&__A__13_D2"
16: "&__A__7/&__A__7_D2"
27: "U31/syn695/U31/syn695_D2"
6: "&__A__14" 17: "&__A__8/&__A__8_D2"
28: "\$Net00001_"
7: "&__A__15" 18: "&__A__9/&__A__9_D2"
29: "\$Net00044_"
8: "&__A__16" 19: "U23/syn2336/U23/syn2336_D2"
30: "\$Net00054_"
9: "&__A__17" 20: "U23/syn2337/U23/syn2337_D2"
31: "\$Net00055_"
10: "&__A__18" 21: "U23/syn2342/U23/syn2342_D2"
32: "\$Net00057_"
11: "&__A__2/&__A__2_D2"
22: "U31/countnum<0>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
&__A__9/&__A__9_D2 ...X...X.X........XXX........X.......... 7 7
&__A__2/&__A__2_D2 X..X.X.X.X.........XX........X.......... 8 8
\$Net00053_ ........................................ 0 0
\$Net00056_ ........................................ 0 0
U31/countnum<3> XXXXX.....XXXXXXXX...XXXXXXX............ 20 20
\$Net00044_ ....X..XXX........X..................... 5 5
\$Net00071_ .....X..XX...................XX......... 5 5
U23/syn2342/U23/syn2342_D2
.....XXXXX..................XXX......... 8 8
U23/syn2337/U23/syn2337_D2
.....XXXXX..........X........XXX........ 9 9
&__A__7/&__A__7_D2 ....X.XXXX..........X........XX......... 8 8
&__A__6/&__A__6_D2 ......XXXX.....X....X........XX......... 8 8
&__A__5/&__A__5_D2 .....XXXXX........X.X........X.......... 8 8
&__A__1/&__A__1_D2 ...X....XX........X.X.........XX........ 7 7
&__A__4/&__A__4_D2 ..XX.XXXX.........XXX........XX......... 11 11
&__A__10/&__A__10_D2
....X.XXXX.X.......X.........X.......... 8 8
&__A__8/&__A__8_D2 .....XXXXX........X.........XX.......... 8 8
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 32/4
Number of signals used by logic mapping into function block: 32
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 /\4 1 FB5_1 (b) (b)
(unused) 0 0 0 5 FB5_2 32 I/O
(unused) 0 0 0 5 FB5_3 33 I/O
(unused) 0 0 0 5 FB5_4 (b)
U20/time<5> 2 0 0 3 FB5_5 STD 34 I/O (b)
U20/time<4> 2 0 0 3 FB5_6 STD 35 I/O (b)
U20/time<3> 2 0 0 3 FB5_7 STD (b) (b)
U20/time<2> 2 0 0 3 FB5_8 STD 36 I/O (b)
U20/time<1> 2 0 0 3 FB5_9 STD 37 I/O I
U20/time<0> 2 0 0 3 FB5_10 STD (b) (b)
U20/syn8093/U20/syn8093_D
2 0 0 3 FB5_11 STD 39 I/O I
BUF_U20/time<4> 2 0 0 3 FB5_12 STD 40 I/O I
$OpTx$FX_SC$306 2 0 0 3 FB5_13 STD (b) (b)
$OpTx$FX_DC$326 2 0 0 3 FB5_14 STD 41 I/O I
U31/syn4535/U31/syn4535_D2
3 0 0 2 FB5_15 STD 43 I/O I
U20/syn7160/U20/syn7160_D2
3 0 0 2 FB5_16 STD (b) (b)
U20/C459/C2/C3/U20/C459/C2/C3_D2
4 0 \/1 0 FB5_17 STD 44 I/O I
&__A__18 10 5<- 0 0 FB5_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "$OpTx$FX_DC$326" 12: "\$Net00061_" 23: "U20/C459/C4/C3/U20/C459/C4/C3_D2"
2: "$OpTx$FX_DC$330" 13: "\$Net00064_" 24: "U20/syn8093/U20/syn8093_D"
3: "$OpTx$FX_SC$306" 14: "\$Net00041_" 25: "U20/time<0>"
4: "&__A__13/&__A__13_D2"
15: "\$Net00060_" 26: "U20/time<1>"
5: "&__A__14" 16: "\$Net00049_" 27: "U20/time<2>"
6: "&__A__15" 17: "\$Net00042_" 28: "U20/time<3>"
7: "&__A__18" 18: "\$Net00043_" 29: "U20/time<4>"
8: "BUF_U20/time<4>" 19: "\$Net00045_" 30: "U20/time<5>"
9: "\$Net00062_" 20: "\$Net00046_" 31: "U31/countnum<12>"
10: "\$Net00051_" 21: "\$Net00047_" 32: "\$Net00068_"
11: "\$Net00050_" 22: "\$Net00048_"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
U20/time<5> ........................XXXXX..X........ 6 6
U20/time<4> .......X.......................X........ 2 2
U20/time<3> ........................XXX....X........ 4 4
U20/time<2> ........................XX.....X........ 3 3
U20/time<1> ........................X......X........ 2 2
U20/time<0> ........................X......X........ 2 2
U20/syn8093/U20/syn8093_D
....X......X..XX........................ 4 4
BUF_U20/time<4> ........................XXXXX........... 5 5
$OpTx$FX_SC$306 ........XXXXXXXXXXXXXX.................. 14 14
$OpTx$FX_DC$326 ........................XXX............. 3 3
U31/syn4535/U31/syn4535_D2
.X.X..........................X......... 3 3
U20/syn7160/U20/syn7160_D2
........XXXXXXXXXXXXXX.................. 14 14
U20/C459/C2/C3/U20/C459/C2/C3_D2
.....X.....X..XX.......X................ 5 5
&__A__18 X.X...XXXXXXXXXXXXXXXXX....X.X.X........ 22 22
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 33/3
Number of signals used by logic mapping into function block: 33
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
$OpTx$FX_DC$299 9 4<- 0 0 FB6_1 STD (b) (b)
\$Net00068_ 1 0 /\4 0 FB6_2 STD 45 I/O I
(unused) 0 0 0 5 FB6_3 46 I/O I
(unused) 0 0 0 5 FB6_4 (b)
(unused) 0 0 0 5 FB6_5 47 I/O I
(unused) 0 0 0 5 FB6_6 48 I/O I
\$Net00001_ 1 0 0 4 FB6_7 STD (b) (b)
U33/countnum 1 0 0 4 FB6_8 STD 50 I/O I
U31/syn665/U31/syn665_D2
1 0 0 4 FB6_9 STD 51 I/O I
U1/count 1 0 0 4 FB6_10 STD (b) (b)
$OpTx$FX_DC$290 1 0 \/4 0 FB6_11 STD 52 I/O I
U31/syn4395/U31/syn4395_D2
7 4<- \/2 0 FB6_12 STD 53 I/O I
$OpTx$FX_DC$330 7 2<- 0 0 FB6_13 STD (b) (b)
(unused) 0 0 \/5 0 FB6_14 54 I/O (b)
$OpTx$FX_DC$311 7 5<- \/3 0 FB6_15 STD 55 I/O (b)
U31/syn4485/U31/syn4485_D2
8 3<- 0 0 FB6_16 STD (b) (b)
(unused) 0 0 \/3 2 FB6_17 56 I/O (b)
U31/syn3879/U31/syn3879_D2
8 3<- 0 0 FB6_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "$OpTx$FX_DC$272" 12: "&__A__5/&__A__5_D2"
23: "U31/countnum<3>"
2: "$OpTx$FX_DC$273" 13: "&__A__6/&__A__6_D2"
24: "U31/countnum<4>"
3: "$OpTx$FX_DC$279" 14: "&__A__7/&__A__7_D2"
25: "U31/countnum<5>"
4: "$OpTx$FX_DC$290" 15: "&__A__8/&__A__8_D2"
26: "U31/countnum<6>"
5: "$OpTx$FX_DC$299" 16: "&__A__9/&__A__9_D2"
27: "U31/countnum<7>"
6: "$OpTx$FX_DC$311" 17: "U1/count" 28: "U31/countnum<8>"
7: "$OpTx$FX_DC$347" 18: "U31/countnum<0>" 29: "U31/countnum<9>"
8: "&__A__10/&__A__10_D2"
19: "U31/countnum<10>"
30: "U31/syn3879/U31/syn3879_D2"
9: "&__A__11/&__A__11_D2"
20: "U31/countnum<11>"
31: "U31/syn4464/U31/syn4464_D2"
10: "&__A__12/&__A__12_D2"
21: "U31/countnum<1>" 32: "U31/syn4485/U31/syn4485_D2"
11: "&__A__4/&__A__4_D2"
22: "U31/countnum<2>" 33: "U33/countnum"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
$OpTx$FX_DC$299 .X.X...X.....XXX.........XXXX..X........ 11 11
\$Net00068_ ................................X....... 1 1
\$Net00001_ ................X....................... 1 1
U33/countnum ................................X....... 1 1
U31/syn665/U31/syn665_D2
.................X..XXXXXXX............. 8 8
U1/count ................X....................... 1 1
$OpTx$FX_DC$290 .......X....................X........... 2 2
U31/syn4395/U31/syn4395_D2
.......XX..................XXX.......... 5 5
$OpTx$FX_DC$330 ....X...XX........XX.................... 5 5
$OpTx$FX_DC$311 ......X....XX.........XX................ 5 5
U31/syn4485/U31/syn4485_D2
X.........XXX.........XXX.....X......... 8 8
U31/syn3879/U31/syn3879_D2
..X..X.......XXX........XXX............. 8 8
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
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