piano.rpt

这是一个用vhdl写的电子琴的小程序（整个工程文件）

U31/countnum<0>      XXXXXXXXXXXXXX...........X....X......... 16      16
U31/countnum<9>      XXXXXXXXXXXXX.........XX.XXX..X......... 19      19
U31/countnum<8>      XXXXXXXXXXXXX.........X..X.X..X......... 17      17
U31/countnum<7>      XXXXXXXXXXXXX.......XX...X.XX.X......... 19      19
U31/countnum<6>      XXXXXXXXXXXXX.......X....X..X.X......... 17      17
U31/countnum<5>      XXXXXXXXXXXXX.....XX.....X..XXX......... 19      19
U31/countnum<4>      XXXXXXXXXXXXX.....X......X...XX......... 17      17
U31/countnum<1>      XXXXXXXXXXXXXX...X.......X....X......... 17      17
\$Net00037_          XXXXXXXXXXXXX.XXX.......X.....XX........ 19      19
U31/countnum<12>     XXXXXXXXXXXXX.XXX........XX...X......... 19      19
U31/countnum<10>     XXXXXXXXXXXXX.X..........XX...X......... 17      17
U31/countnum<11>     XXXXXXXXXXXXX.XX.........XX...X......... 18      18
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               31/5
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0   /\1   4     FB2_1               (b)     (b)
(unused)              0       0   \/5   0     FB2_2         71    I/O     (b)
&__A__17             17      12<-   0   0     FB2_3   STD   72    I/O     (b)
(unused)              0       0   /\5   0     FB2_4               (b)     (b)
U20/syn7164/U20/syn7164_D2
                      4       1<- /\2   0     FB2_5   STD   74    GSR/I/O (b)
(unused)              0       0   /\1   4     FB2_6         75    I/O     (b)
(unused)              0       0   \/3   2     FB2_7               (b)     (b)
(unused)              0       0   \/5   0     FB2_8         76    GTS/I/O (b)
&__A__16             18      13<-   0   0     FB2_9   STD   77    GTS/I/O (b)
(unused)              0       0   /\5   0     FB2_10              (b)     (b)
(unused)              0       0   \/5   0     FB2_11        79    I/O     (b)
(unused)              0       0   \/5   0     FB2_12        80    I/O     (b)
&__A__14             20      15<-   0   0     FB2_13  STD         (b)     (b)
(unused)              0       0   /\5   0     FB2_14        81    I/O     (b)
(unused)              0       0   \/5   0     FB2_15        82    I/O     (b)
(unused)              0       0   \/5   0     FB2_16        83    I/O     (b)
&__A__15             21      16<-   0   0     FB2_17  STD   84    I/O     (b)
(unused)              0       0   /\5   0     FB2_18              (b)     (b)

Signals Used by Logic in Function Block
  1: "$OpTx$FX_DC$326" 12: "\$Net00041_"     22: "U20/syn7160/U20/syn7160_D2" 
  2: "$OpTx$FX_SC$306" 13: "\$Net00060_"     23: "U20/syn7164/U20/syn7164_D2" 
  3: "&__A__15"        14: "\$Net00049_"     24: "U20/syn8093/U20/syn8093_D" 
  4: "&__A__16"        15: "\$Net00042_"     25: "U20/time<0>" 
  5: "&__A__17"        16: "\$Net00043_"     26: "U20/time<1>" 
  6: "BUF_U20/time<4>" 17: "\$Net00045_"     27: "U20/time<2>" 
  7: "\$Net00062_"     18: "\$Net00046_"     28: "U20/time<3>" 
  8: "\$Net00051_"     19: "\$Net00047_"     29: "U20/time<4>" 
  9: "\$Net00050_"     20: "\$Net00048_"     30: "U20/time<5>" 
 10: "\$Net00061_"     21: "U20/C459/C2/C3/U20/C459/C2/C3_D2" 
                                             31: "\$Net00068_" 
 11: "\$Net00064_"    

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
&__A__17             XXXXXXXXXXXXXXXXXXXXXX..XXXXXXX......... 29      29
U20/syn7164/U20/syn7164_D2 
                     ......XXXXXXXXXXXXXX.................... 14      14
&__A__16             XX.X.XXXXXXXXXXXXXXXXX..XXXXXXX......... 27      27
&__A__14             X....XXXXXXXXXXXXXXX.XXXXXXXXXX......... 26      26
&__A__15             XXX..XXXXXXXXXXXXXXX..XXXXXXXXX......... 27      27
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining:               32/4
Number of signals used by logic mapping into function block:  32
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
$OpTx$FX_DC$347       7       2<-   0   0     FB3_1   STD         (b)     (b)
(unused)              0       0   /\2   3     FB3_2         14    I/O     (b)
(unused)              0       0     0   5     FB3_3         15    I/O     
U31/syn695/U31/syn695_D2
                      1       0     0   4     FB3_4   STD         (b)     (b)
$OpTx$FX_DC$279       1       0     0   4     FB3_5   STD   17    I/O     (b)
U20/C459/C4/C3/U20/C459/C4/C3_D2
                      2       0     0   3     FB3_6   STD   18    I/O     (b)
&__A__3/&__A__3_D2    2       0     0   3     FB3_7   STD         (b)     (b)
&__A__13/&__A__13_D2
                      2       0     0   3     FB3_8   STD   19    I/O     (b)
U23/syn2336/U23/syn2336_D2
                      3       0     0   2     FB3_9   STD   20    I/O     (b)
&__A__12/&__A__12_D2
                      3       0     0   2     FB3_10  STD         (b)     (b)
&__A__11/&__A__11_D2
                      4       0     0   1     FB3_11  STD   21    I/O     (b)
\$Net00054_           5       0     0   0     FB3_12  STD   23    I/O     O
U31/countnum<2>       5       0     0   0     FB3_13  STD         (b)     (b)
\$Net00057_           5       0     0   0     FB3_14  STD   24    I/O     O
\$Net00055_           6       1<-   0   0     FB3_15  STD   25    I/O     O
\$Net00058_           0       0   /\1   4     FB3_16  STD   26    I/O     O
(unused)              0       0   \/2   3     FB3_17        31    I/O     (b)
U31/syn4464/U31/syn4464_D2
                      7       2<-   0   0     FB3_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: "&__A__1/&__A__1_D2" 
                       12: "&__A__3/&__A__3_D2" 
                                             23: "U31/countnum<0>" 
  2: "&__A__10/&__A__10_D2" 
                       13: "&__A__4/&__A__4_D2" 
                                             24: "U31/countnum<1>" 
  3: "&__A__11/&__A__11_D2" 
                       14: "&__A__5/&__A__5_D2" 
                                             25: "U31/countnum<2>" 
  4: "&__A__12/&__A__12_D2" 
                       15: "&__A__6/&__A__6_D2" 
                                             26: "U31/countnum<3>" 
  5: "&__A__13/&__A__13_D2" 
                       16: "&__A__7/&__A__7_D2" 
                                             27: "U31/countnum<7>" 
  6: "&__A__14"        17: "&__A__8/&__A__8_D2" 
                                             28: "U31/syn4535/U31/syn4535_D2" 
  7: "&__A__15"        18: "&__A__9/&__A__9_D2" 
                                             29: "\$Net00001_" 
  8: "&__A__16"        19: "U20/C459/C2/C3/U20/C459/C2/C3_D2" 
                                             30: "\$Net00044_" 
  9: "&__A__17"        20: "U23/syn2336/U23/syn2336_D2" 
                                             31: "\$Net00054_" 
 10: "&__A__18"        21: "U23/syn2337/U23/syn2337_D2" 
                                             32: "\$Net00055_" 
 11: "&__A__2/&__A__2_D2" 
                       22: "U23/syn2342/U23/syn2342_D2" 
                                            

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
$OpTx$FX_DC$347      ..........XXX.........XXX............... 6       6
U31/syn695/U31/syn695_D2 
                     ......................XXXX.............. 4       4
$OpTx$FX_DC$279      .................X........X............. 2       2
U20/C459/C4/C3/U20/C459/C4/C3_D2 
                     ......XXX.........X..................... 4       4
&__A__3/&__A__3_D2   ....XXX..X..........X................... 5       5
&__A__13/&__A__13_D2 
                     .....XXXXX.............................. 5       5
U23/syn2336/U23/syn2336_D2 
                     .....XX.XX....................XX........ 6       6
&__A__12/&__A__12_D2 
                     .....XXXXX.............................. 5       5
&__A__11/&__A__11_D2 
                     ......XXXX.........X..........X......... 6       6
\$Net00054_          .....XXXXX.............................. 5       5
U31/countnum<2>      XXXXX.....XXXXXXXX....XXX..XX........... 18      18
\$Net00057_          .....XXXXX...........X.......X.......... 7       7
\$Net00055_          .....XXXXX.............................. 5       5
\$Net00058_          ........................................ 0       0
U31/syn4464/U31/syn4464_D2 
                     X.........XX..........XXX............... 6       6
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining:               32/4
Number of signals used by logic mapping into function block:  32
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0   /\1   4     FB4_1               (b)     (b)
(unused)              0       0     0   5     FB4_2         57    I/O     
&__A__9/&__A__9_D2    3       0     0   2     FB4_3   STD   58    I/O     (b)
&__A__2/&__A__2_D2    3       0     0   2     FB4_4   STD         (b)     (b)
\$Net00053_           0       0     0   5     FB4_5   STD   61    I/O     O
\$Net00056_           0       0     0   5     FB4_6   STD   62    I/O     O
U31/countnum<3>       4       0     0   1     FB4_7   STD         (b)     (b)
\$Net00044_           3       0     0   2     FB4_8   STD   63    I/O     O
\$Net00071_           3       0     0   2     FB4_9   STD   65    I/O     O
U23/syn2342/U23/syn2342_D2
                      4       0     0   1     FB4_10  STD         (b)     (b)
U23/syn2337/U23/syn2337_D2
                      4       0     0   1     FB4_11  STD   66    I/O     (b)
&__A__7/&__A__7_D2    4       0     0   1     FB4_12  STD   67    I/O     (b)
&__A__6/&__A__6_D2    4       0     0   1     FB4_13  STD         (b)     (b)
&__A__5/&__A__5_D2    4       0     0   1     FB4_14  STD   68    I/O     (b)
&__A__1/&__A__1_D2    4       0     0   1     FB4_15  STD   69    I/O     (b)
&__A__4/&__A__4_D2    5       0     0   0     FB4_16  STD         (b)     (b)
&__A__10/&__A__10_D2
                      5       0     0   0     FB4_17  STD   70    I/O     (b)
&__A__8/&__A__8_D2    6       1<-   0   0     FB4_18  STD         (b)     (b)

Signals Used by Logic in Function Block
  1: "&__A__1/&__A__1_D2" 
                       12: "&__A__3/&__A__3_D2" 
                                             23: "U31/countnum<1>" 
  2: "&__A__10/&__A__10_D2" 
                       13: "&__A__4/&__A__4_D2" 
                                             24: "U31/countnum<2>"