📄 piano.rpt
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cpldfit: version E.30 Xilinx Inc.
Fitter Report
Design Name: piano Date: 12-23-2007, 4:04PM
Device Used: XC95108-15-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
78 /108 ( 72%) 338 /540 ( 62%) 29 /108 ( 26%) 25 /69 ( 36%) 192/216 ( 88%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 14 14 | I/O : 23 40
Output : 9 9 | GCK/IO : 2 1
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 2 2 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 25 25
MACROCELL RESOURCES:
Total Macrocells Available 108
Registered Macrocells 29
Non-registered Macrocell driving I/O 8
GLOBAL RESOURCES:
Signal '"\$Net00040_"' mapped onto global clock net GCK1.
Signal '"\$Net00059_"' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 78 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 78 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
$OpTx$FX_DC$272 1 2 FB1_6 STD 4 I/O (b)
$OpTx$FX_DC$273 1 2 FB1_5 STD 3 I/O (b)
$OpTx$FX_DC$279 1 2 FB3_5 STD 17 I/O (b)
$OpTx$FX_DC$290 1 2 FB6_11 STD 52 I/O I
$OpTx$FX_DC$299 9 11 FB6_1 STD (b) (b)
$OpTx$FX_DC$311 7 5 FB6_15 STD 55 I/O (b)
$OpTx$FX_DC$326 2 3 FB5_14 STD 41 I/O I
$OpTx$FX_DC$330 7 5 FB6_13 STD (b) (b)
$OpTx$FX_DC$347 7 6 FB3_1 STD (b) (b)
$OpTx$FX_SC$306 2 14 FB5_13 STD (b) (b)
&__A__1/&__A__1_D2 4 7 FB4_15 STD 69 I/O (b)
&__A__10/&__A__10_D2 5 8 FB4_17 STD 70 I/O (b)
&__A__11/&__A__11_D2 4 6 FB3_11 STD 21 I/O (b)
&__A__12/&__A__12_D2 3 5 FB3_10 STD (b) (b)
&__A__13/&__A__13_D2 2 5 FB3_8 STD 19 I/O (b)
&__A__14 20 26 FB2_13 STD (b) (b)
&__A__15 21 27 FB2_17 STD 84 I/O (b)
&__A__16 18 27 FB2_9 STD 77 GTS/I/O (b)
&__A__17 17 29 FB2_3 STD 72 I/O (b)
&__A__18 10 22 FB5_18 STD (b) (b)
&__A__2/&__A__2_D2 3 8 FB4_4 STD (b) (b)
&__A__3/&__A__3_D2 2 5 FB3_7 STD (b) (b)
&__A__4/&__A__4_D2 5 11 FB4_16 STD (b) (b)
&__A__5/&__A__5_D2 4 8 FB4_14 STD 68 I/O (b)
&__A__6/&__A__6_D2 4 8 FB4_13 STD (b) (b)
&__A__7/&__A__7_D2 4 8 FB4_12 STD 67 I/O (b)
&__A__8/&__A__8_D2 6 8 FB4_18 STD (b) (b)
&__A__9/&__A__9_D2 3 7 FB4_3 STD 58 I/O (b)
BUF_U20/time<4> 2 5 FB5_12 STD 40 I/O I
U1/count 1 1 FB6_10 STD (b) (b)
U20/C459/C2/C3/U20/C459/C2/C3_D2 4 5 FB5_17 STD 44 I/O I
U20/C459/C4/C3/U20/C459/C4/C3_D2 2 4 FB3_6 STD 18 I/O (b)
U20/syn7160/U20/syn7160_D2 3 14 FB5_16 STD (b) (b)
U20/syn7164/U20/syn7164_D2 4 14 FB2_5 STD 74 GSR/I/O (b)
U20/syn8093/U20/syn8093_D 2 4 FB5_11 STD 39 I/O I
U20/time<0> 2 2 FB5_10 STD (b) (b)
U20/time<1> 2 2 FB5_9 STD 37 I/O I
U20/time<2> 2 3 FB5_8 STD 36 I/O (b)
U20/time<3> 2 4 FB5_7 STD (b) (b)
U20/time<4> 2 2 FB5_6 STD 35 I/O (b)
U20/time<5> 2 6 FB5_5 STD 34 I/O (b)
U23/syn2336/U23/syn2336_D2 3 6 FB3_9 STD 20 I/O (b)
U23/syn2337/U23/syn2337_D2 4 9 FB4_11 STD 66 I/O (b)
U23/syn2342/U23/syn2342_D2 4 8 FB4_10 STD (b) (b)
U31/countnum<0> 3 16 FB1_7 STD (b) (b)
U31/countnum<10> 4 17 FB1_17 STD 13 I/O (b)
U31/countnum<11> 5 18 FB1_18 STD (b) (b)
U31/countnum<12> 4 19 FB1_16 STD 12 GCK/I/O GCK
U31/countnum<1> 4 17 FB1_14 STD 10 GCK/I/O (b)
U31/countnum<2> 5 18 FB3_13 STD (b) (b)
U31/countnum<3> 4 20 FB4_7 STD (b) (b)
U31/countnum<4> 4 17 FB1_13 STD (b) (b)
U31/countnum<5> 4 19 FB1_12 STD 9 GCK/I/O GCK
U31/countnum<6> 4 17 FB1_11 STD 7 I/O (b)
U31/countnum<7> 4 19 FB1_10 STD (b) (b)
U31/countnum<8> 4 17 FB1_9 STD 6 I/O (b)
U31/countnum<9> 4 19 FB1_8 STD 5 I/O (b)
U31/syn3879/U31/syn3879_D2 8 8 FB6_18 STD (b) (b)
U31/syn4395/U31/syn4395_D2 7 5 FB6_12 STD 53 I/O I
U31/syn4464/U31/syn4464_D2 7 6 FB3_18 STD (b) (b)
U31/syn4485/U31/syn4485_D2 8 8 FB6_16 STD (b) (b)
U31/syn4535/U31/syn4535_D2 3 3 FB5_15 STD 43 I/O I
U31/syn650/U31/syn650_D2 1 3 FB1_4 STD (b) (b)
U31/syn665/U31/syn665_D2 1 8 FB6_9 STD 51 I/O I
U31/syn680/U31/syn680_D2 1 3 FB1_3 STD 2 I/O (b)
U31/syn695/U31/syn695_D2 1 4 FB3_4 STD (b) (b)
U33/countnum 1 1 FB6_8 STD 50 I/O I
\$Net00001_ 1 1 FB6_7 STD (b) (b)
\$Net00037_ 9 19 FB1_15 STD FAST 11 I/O O
\$Net00044_ 3 5 FB4_8 STD FAST 63 I/O O
\$Net00053_ 0 0 FB4_5 STD FAST 61 I/O O
\$Net00054_ 5 5 FB3_12 STD FAST 23 I/O O
\$Net00055_ 6 5 FB3_15 STD FAST 25 I/O O
\$Net00056_ 0 0 FB4_6 STD FAST 62 I/O O
\$Net00057_ 5 7 FB3_14 STD FAST 24 I/O O
\$Net00058_ 0 0 FB3_16 STD FAST 26 I/O O
\$Net00068_ 1 1 FB6_2 STD 45 I/O I
\$Net00071_ 3 5 FB4_9 STD FAST 65 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
\$Net00040_ FB1_12 9 GCK/I/O GCK
\$Net00041_ FB5_11 39 I/O I
\$Net00042_ FB5_15 43 I/O I
\$Net00043_ FB5_17 44 I/O I
\$Net00045_ FB6_2 45 I/O I
\$Net00046_ FB6_3 46 I/O I
\$Net00047_ FB6_5 47 I/O I
\$Net00048_ FB6_6 48 I/O I
\$Net00049_ FB5_14 41 I/O I
\$Net00050_ FB6_9 51 I/O I
\$Net00051_ FB6_8 50 I/O I
\$Net00059_ FB1_16 12 GCK/I/O GCK
\$Net00060_ FB5_12 40 I/O I
\$Net00061_ FB6_11 52 I/O I
\$Net00062_ FB5_9 37 I/O I
\$Net00064_ FB6_12 53 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 16 32 32 57 1/0 12
FB2 5 31 31 80 0/0 12
FB3 15 32 32 53 4/0 12
FB4 16 32 32 56 4/0 11
FB5 14 32 32 40 0/0 11
FB6 12 33 33 52 0/0 11
---- ----- ----- -----
78 338 9/0 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 32/4
Number of signals used by logic mapping into function block: 32
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
(unused) 0 0 0 5 FB1_2 1 I/O
U31/syn680/U31/syn680_D2
1 0 0 4 FB1_3 STD 2 I/O (b)
U31/syn650/U31/syn650_D2
1 0 0 4 FB1_4 STD (b) (b)
$OpTx$FX_DC$273 1 0 0 4 FB1_5 STD 3 I/O (b)
$OpTx$FX_DC$272 1 0 0 4 FB1_6 STD 4 I/O (b)
U31/countnum<0> 3 0 0 2 FB1_7 STD (b) (b)
U31/countnum<9> 4 0 0 1 FB1_8 STD 5 I/O (b)
U31/countnum<8> 4 0 0 1 FB1_9 STD 6 I/O (b)
U31/countnum<7> 4 0 0 1 FB1_10 STD (b) (b)
U31/countnum<6> 4 0 0 1 FB1_11 STD 7 I/O (b)
U31/countnum<5> 4 0 0 1 FB1_12 STD 9 GCK/I/O GCK
U31/countnum<4> 4 0 \/1 0 FB1_13 STD (b) (b)
U31/countnum<1> 4 1<- \/2 0 FB1_14 STD 10 GCK/I/O (b)
\$Net00037_ 9 4<- 0 0 FB1_15 STD 11 I/O O
U31/countnum<12> 4 1<- /\2 0 FB1_16 STD 12 GCK/I/O GCK
U31/countnum<10> 4 0 /\1 0 FB1_17 STD 13 I/O (b)
U31/countnum<11> 5 0 0 0 FB1_18 STD (b) (b)
Signals Used by Logic in Function Block
1: "&__A__1/&__A__1_D2"
12: "&__A__8/&__A__8_D2"
23: "U31/countnum<8>"
2: "&__A__10/&__A__10_D2"
13: "&__A__9/&__A__9_D2"
24: "U31/countnum<9>"
3: "&__A__11/&__A__11_D2"
14: "U31/countnum<0>" 25: "U31/syn4395/U31/syn4395_D2"
4: "&__A__12/&__A__12_D2"
15: "U31/countnum<10>"
26: "U31/syn4535/U31/syn4535_D2"
5: "&__A__13/&__A__13_D2"
16: "U31/countnum<11>"
27: "U31/syn650/U31/syn650_D2"
6: "&__A__2/&__A__2_D2"
17: "U31/countnum<12>"
28: "U31/syn665/U31/syn665_D2"
7: "&__A__3/&__A__3_D2"
18: "U31/countnum<1>" 29: "U31/syn680/U31/syn680_D2"
8: "&__A__4/&__A__4_D2"
19: "U31/countnum<4>" 30: "U31/syn695/U31/syn695_D2"
9: "&__A__5/&__A__5_D2"
20: "U31/countnum<5>" 31: "\$Net00001_"
10: "&__A__6/&__A__6_D2"
21: "U31/countnum<6>" 32: "\$Net00037_"
11: "&__A__7/&__A__7_D2"
22: "U31/countnum<7>"
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
U31/syn680/U31/syn680_D2
..................XX.........X.......... 3 3
U31/syn650/U31/syn650_D2
......................XX...X............ 3 3
$OpTx$FX_DC$273 ............X.........X................. 2 2
$OpTx$FX_DC$272 .........X.........X.................... 2 2
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