📄 piano.mfd

📁 这是一个用vhdl写的电子琴的小程序（整个工程文件）
💻 MFD
📖 第 1 页 / 共 5 页
字号:
上一页 1 2 3 45
INPUTS | 6 | \$Net00054_  | \$Net00055_  | &__A__17  | &__A__14  | &__A__15  | &__A__18
INPUTMC | 6 | 2 | 11 | 2 | 14 | 1 | 2 | 1 | 12 | 1 | 16 | 4 | 17
EQ | 4 | 
    "U23/syn2336/U23/syn2336_D2"  =  /"\$Net00054_" * "\$Net00055_" * "&__A__17"
	+ /"\$Net00055_" * "&__A__14" * "&__A__15"
	+ /"\$Net00054_" * "\$Net00055_" * /"&__A__15" * 
	/"&__A__18"

MACROCELL | 3 | 9 | U23/syn2342/U23/syn2342_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 9 | 2 | 13 | 3 | 11 | 3 | 2 | 3 | 10 | 3 | 3 | 3 | 14 | 3 | 15 | 3 | 13 | 3 | 12
INPUTS | 8 | \$Net00054_  | \$Net00055_  | &__A__16  | \$Net00044_  | &__A__15  | &__A__18  | &__A__14  | &__A__17
INPUTMC | 8 | 2 | 11 | 2 | 14 | 1 | 8 | 3 | 7 | 1 | 16 | 4 | 17 | 1 | 12 | 1 | 2
EQ | 6 | 
    "U23/syn2342/U23/syn2342_D2"  =  /"\$Net00044_" * /"&__A__15" * "&__A__16"
	+ /"\$Net00054_" * "\$Net00055_" * /"&__A__16"
	+ "\$Net00044_" * "\$Net00055_" * "&__A__15" * 
	/"&__A__18"
	+ "&__A__14" * /"&__A__15" * "&__A__16" * 
	/"&__A__17"

MACROCELL | 3 | 11 | &__A__7/&__A__7_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 17 | 5 | 17 | 0 | 6 | 5 | 0 | 3 | 6 | 0 | 11 | 0 | 9 | 0 | 7 | 0 | 16 | 0 | 17 | 2 | 12 | 0 | 12 | 0 | 10 | 0 | 8 | 3 | 12 | 0 | 15 | 5 | 1 | 5 | 16
INPUTS | 8 | U23/syn2342/U23/syn2342_D2  | &__A__15  | &__A__16  | &__A__17  | \$Net00055_  | &__A__18  | &__A__13/&__A__13_D2  | \$Net00054_
INPUTMC | 8 | 3 | 9 | 1 | 16 | 1 | 8 | 1 | 2 | 2 | 14 | 4 | 17 | 2 | 7 | 2 | 11
EQ | 6 | 
    "&__A__7/&__A__7_D2"  =  "U23/syn2342/U23/syn2342_D2"
	+ /"&__A__15" * "&__A__16" * /"&__A__17"
	+ "\$Net00054_" * "\$Net00055_" * "&__A__15" * 
	/"&__A__18"
	+ /"\$Net00055_" * /"&__A__16" * /"&__A__18" * 
	/"&__A__13/&__A__13_D2"

MACROCELL | 3 | 17 | &__A__8/&__A__8_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 15 | 5 | 17 | 0 | 6 | 5 | 0 | 3 | 6 | 0 | 11 | 0 | 9 | 0 | 7 | 0 | 16 | 0 | 17 | 2 | 12 | 0 | 12 | 0 | 10 | 0 | 8 | 0 | 15 | 5 | 1
INPUTS | 9 | U23/syn2336/U23/syn2336_D2  | \$Net00044_  | \$Net00054_  | &__A__15  | &__A__16  | &__A__18  | &__A__14  | &__A__17  | EXP15_.EXP
INPUTMC | 9 | 2 | 8 | 3 | 7 | 2 | 11 | 1 | 16 | 1 | 8 | 4 | 17 | 1 | 12 | 1 | 2 | 3 | 0
IMPORTS | 1 | 3 | 0
EQ | 11 | 
    "&__A__8/&__A__8_D2"  =  "U23/syn2336/U23/syn2336_D2"
	+ /"\$Net00044_" * "\$Net00054_" * "&__A__15"
	+ /"\$Net00054_" * /"&__A__15" * "&__A__16" * 
	"&__A__18"
	+ "&__A__14" * /"&__A__15" * /"&__A__16" * 
	/"&__A__17"
	+ "\$Net00054_" * /"&__A__14" * "&__A__15" * 
	"&__A__16" * /"&__A__18"
;Imported pterms FB4_1
	+ /"&__A__14" * "&__A__15" * /"&__A__16" * 
	/"&__A__17" * /"&__A__18"

MACROCELL | 3 | 2 | &__A__9/&__A__9_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 16 | 5 | 0 | 0 | 6 | 0 | 4 | 3 | 6 | 0 | 11 | 0 | 9 | 0 | 7 | 0 | 16 | 0 | 17 | 2 | 12 | 0 | 12 | 0 | 10 | 0 | 8 | 2 | 4 | 5 | 17 | 0 | 15
INPUTS | 7 | &__A__16  | U23/syn2336/U23/syn2336_D2  | U23/syn2337/U23/syn2337_D2  | \$Net00054_  | &__A__18  | U23/syn2342/U23/syn2342_D2  | &__A__12/&__A__12_D2
INPUTMC | 7 | 1 | 8 | 2 | 8 | 3 | 10 | 2 | 11 | 4 | 17 | 3 | 9 | 2 | 9
EQ | 5 | 
    "&__A__9/&__A__9_D2"  =  /"\$Net00054_" * "&__A__16" * /"&__A__18"
	+ /"&__A__16" * /"U23/syn2336/U23/syn2336_D2" * 
	"U23/syn2337/U23/syn2337_D2"
	+ "\$Net00054_" * /"U23/syn2342/U23/syn2342_D2" * 
	/"U23/syn2337/U23/syn2337_D2" * "&__A__12/&__A__12_D2"

MACROCELL | 3 | 10 | U23/syn2337/U23/syn2337_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 5 | 3 | 2 | 3 | 16 | 2 | 6 | 3 | 3 | 3 | 15
INPUTS | 9 | &__A__16  | U23/syn2342/U23/syn2342_D2  | \$Net00057_  | \$Net00054_  | \$Net00055_  | &__A__18  | &__A__15  | &__A__17  | &__A__14
INPUTMC | 9 | 1 | 8 | 3 | 9 | 2 | 13 | 2 | 11 | 2 | 14 | 4 | 17 | 1 | 16 | 1 | 2 | 1 | 12
EQ | 7 | 
    "U23/syn2337/U23/syn2337_D2"  =  /"&__A__16" * "U23/syn2342/U23/syn2342_D2"
	+ "\$Net00057_" * "\$Net00054_" * /"\$Net00055_" * 
	/"&__A__18"
	+ "&__A__14" * /"&__A__16" * /"&__A__17" * 
	"&__A__18"
	+ /"&__A__15" * "&__A__16" * /"&__A__17" * 
	/"U23/syn2342/U23/syn2342_D2"

MACROCELL | 2 | 9 | &__A__12/&__A__12_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 19 | 0 | 14 | 0 | 6 | 5 | 12 | 3 | 6 | 0 | 11 | 0 | 9 | 0 | 7 | 0 | 16 | 0 | 17 | 2 | 12 | 0 | 12 | 0 | 10 | 0 | 8 | 0 | 13 | 3 | 2 | 3 | 3 | 3 | 14 | 3 | 15 | 0 | 15
INPUTS | 5 | &__A__16  | &__A__17  | &__A__18  | &__A__15  | &__A__14
INPUTMC | 5 | 1 | 8 | 1 | 2 | 4 | 17 | 1 | 16 | 1 | 12
EQ | 5 | 
    "&__A__12/&__A__12_D2"  =  "&__A__16" * /"&__A__17" * /"&__A__18"
	+ "&__A__14" * "&__A__15" * /"&__A__17" * 
	/"&__A__18"
	+ /"&__A__15" * /"&__A__16" * "&__A__17" * 
	/"&__A__18"

MACROCELL | 2 | 10 | &__A__11/&__A__11_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 16 | 5 | 11 | 0 | 6 | 5 | 12 | 3 | 6 | 0 | 11 | 0 | 9 | 0 | 7 | 0 | 16 | 0 | 17 | 2 | 12 | 0 | 12 | 0 | 10 | 0 | 8 | 3 | 15 | 0 | 15 | 5 | 10
INPUTS | 6 | U23/syn2336/U23/syn2336_D2  | &__A__15  | &__A__16  | &__A__18  | &__A__17  | \$Net00054_
INPUTMC | 6 | 2 | 8 | 1 | 16 | 1 | 8 | 4 | 17 | 1 | 2 | 2 | 11
EQ | 5 | 
    "&__A__11/&__A__11_D2"  =  "U23/syn2336/U23/syn2336_D2"
	+ "&__A__15" * "&__A__17" * /"&__A__18"
	+ /"&__A__15" * "&__A__16" * /"&__A__18"
	+ /"\$Net00054_" * /"&__A__15" * /"&__A__16" * 
	"&__A__18"

MACROCELL | 3 | 16 | &__A__10/&__A__10_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 15 | 5 | 0 | 0 | 6 | 5 | 10 | 3 | 6 | 0 | 11 | 0 | 9 | 0 | 7 | 0 | 16 | 0 | 17 | 2 | 12 | 0 | 12 | 0 | 10 | 0 | 8 | 5 | 11 | 0 | 15
INPUTS | 8 | U23/syn2337/U23/syn2337_D2  | \$Net00054_  | &__A__13/&__A__13_D2  | &__A__15  | &__A__16  | &__A__18  | &__A__3/&__A__3_D2  | &__A__17
INPUTMC | 8 | 3 | 10 | 2 | 11 | 2 | 7 | 1 | 16 | 1 | 8 | 4 | 17 | 2 | 6 | 1 | 2
EQ | 8 | 
    "&__A__10/&__A__10_D2"  =  "U23/syn2337/U23/syn2337_D2"
	+ "\$Net00054_" * "&__A__13/&__A__13_D2"
	+ /"\$Net00054_" * "&__A__15" * "&__A__16" * 
	/"&__A__18"
	+ "\$Net00054_" * /"&__A__15" * "&__A__16" * 
	/"&__A__17" * /"&__A__3/&__A__3_D2"
	+ "\$Net00054_" * /"&__A__15" * "&__A__16" * 
	/"&__A__18" * /"&__A__3/&__A__3_D2"

MACROCELL | 2 | 6 | &__A__3/&__A__3_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 17 | 2 | 0 | 0 | 6 | 2 | 17 | 3 | 6 | 0 | 11 | 0 | 9 | 0 | 7 | 0 | 16 | 0 | 17 | 2 | 12 | 0 | 12 | 0 | 10 | 0 | 8 | 3 | 16 | 0 | 15 | 2 | 1 | 2 | 16
INPUTS | 5 | &__A__14  | &__A__15  | &__A__18  | &__A__13/&__A__13_D2  | U23/syn2337/U23/syn2337_D2
INPUTMC | 5 | 1 | 12 | 1 | 16 | 4 | 17 | 2 | 7 | 3 | 10
EQ | 3 | 
    "&__A__3/&__A__3_D2"  =  "U23/syn2337/U23/syn2337_D2"
	+ "&__A__14" * /"&__A__15" * /"&__A__18" * 
	/"&__A__13/&__A__13_D2"

MACROCELL | 3 | 3 | &__A__2/&__A__2_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 15 | 2 | 0 | 0 | 6 | 2 | 17 | 3 | 6 | 0 | 11 | 0 | 9 | 0 | 7 | 0 | 16 | 0 | 17 | 2 | 12 | 0 | 12 | 0 | 10 | 0 | 8 | 0 | 15 | 2 | 1
INPUTS | 8 | &__A__14  | U23/syn2337/U23/syn2337_D2  | &__A__12/&__A__12_D2  | &__A__1/&__A__1_D2  | \$Net00054_  | &__A__16  | &__A__18  | U23/syn2342/U23/syn2342_D2
INPUTMC | 8 | 1 | 12 | 3 | 10 | 2 | 9 | 3 | 14 | 2 | 11 | 1 | 8 | 4 | 17 | 3 | 9
EQ | 4 | 
    "&__A__2/&__A__2_D2"  =  /"&__A__14" * "U23/syn2337/U23/syn2337_D2"
	+ "&__A__12/&__A__12_D2" * "&__A__1/&__A__1_D2"
	+ "\$Net00054_" * "&__A__16" * /"&__A__18" * 
	/"U23/syn2342/U23/syn2342_D2"

MACROCELL | 3 | 14 | &__A__1/&__A__1_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 15 | 3 | 3 | 0 | 6 | 2 | 17 | 3 | 6 | 0 | 11 | 0 | 9 | 0 | 7 | 0 | 16 | 0 | 17 | 2 | 12 | 0 | 12 | 0 | 10 | 0 | 8 | 0 | 15 | 2 | 16
INPUTS | 7 | U23/syn2336/U23/syn2336_D2  | U23/syn2342/U23/syn2342_D2  | \$Net00055_  | &__A__12/&__A__12_D2  | \$Net00057_  | &__A__17  | &__A__18
INPUTMC | 7 | 2 | 8 | 3 | 9 | 2 | 14 | 2 | 9 | 2 | 13 | 1 | 2 | 4 | 17
EQ | 7 | 
    "&__A__1/&__A__1_D2"  =  /"\$Net00055_" * "&__A__12/&__A__12_D2"
	+ "U23/syn2336/U23/syn2336_D2" * 
	"U23/syn2342/U23/syn2342_D2"
	+ /"\$Net00057_" * /"&__A__17" * 
	/"U23/syn2342/U23/syn2342_D2"
	+ "\$Net00057_" * "&__A__17" * /"&__A__18" * 
	/"U23/syn2336/U23/syn2336_D2"

MACROCELL | 3 | 15 | &__A__4/&__A__4_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 16 | 2 | 0 | 0 | 6 | 5 | 15 | 3 | 6 | 0 | 11 | 0 | 9 | 0 | 7 | 0 | 16 | 0 | 17 | 2 | 12 | 0 | 12 | 0 | 10 | 0 | 8 | 0 | 15 | 2 | 1 | 5 | 14
INPUTS | 11 | U23/syn2336/U23/syn2336_D2  | \$Net00054_  | &__A__12/&__A__12_D2  | \$Net00055_  | &__A__16  | U23/syn2337/U23/syn2337_D2  | &__A__15  | U23/syn2342/U23/syn2342_D2  | &__A__11/&__A__11_D2  | &__A__14  | &__A__17
INPUTMC | 11 | 2 | 8 | 2 | 11 | 2 | 9 | 2 | 14 | 1 | 8 | 3 | 10 | 1 | 16 | 3 | 9 | 2 | 10 | 1 | 12 | 1 | 2
EQ | 8 | 
    "&__A__4/&__A__4_D2"  =  "U23/syn2336/U23/syn2336_D2"
	+ /"\$Net00054_" * "&__A__12/&__A__12_D2"
	+ "\$Net00055_" * /"&__A__16" * 
	"U23/syn2337/U23/syn2337_D2"
	+ /"&__A__15" * /"U23/syn2342/U23/syn2342_D2" * 
	"&__A__11/&__A__11_D2"
	+ "&__A__14" * /"&__A__15" * /"&__A__17" * 
	/"U23/syn2337/U23/syn2337_D2" * /"&__A__12/&__A__12_D2"

MACROCELL | 3 | 13 | &__A__5/&__A__5_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 15 | 5 | 14 | 0 | 6 | 5 | 15 | 3 | 6 | 0 | 11 | 0 | 9 | 0 | 7 | 0 | 16 | 0 | 17 | 2 | 12 | 0 | 12 | 0 | 10 | 0 | 8 | 0 | 15 | 5 | 13
INPUTS | 8 | U23/syn2342/U23/syn2342_D2  | \$Net00054_  | &__A__16  | &__A__18  | U23/syn2336/U23/syn2336_D2  | &__A__14  | &__A__17  | &__A__15
INPUTMC | 8 | 3 | 9 | 2 | 11 | 1 | 8 | 4 | 17 | 2 | 8 | 1 | 12 | 1 | 2 | 1 | 16
EQ | 7 | 
    "&__A__5/&__A__5_D2"  =  "U23/syn2342/U23/syn2342_D2"
	+ "\$Net00054_" * /"&__A__15" * "&__A__17" * 
	/"&__A__18"
	+ /"\$Net00054_" * "&__A__16" * /"&__A__18" * 
	/"U23/syn2336/U23/syn2336_D2"
	+ "&__A__14" * /"&__A__16" * /"&__A__17" * 
	"&__A__18"

MACROCELL | 3 | 12 | &__A__6/&__A__6_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 16 | 5 | 15 | 0 | 6 | 0 | 5 | 3 | 6 | 0 | 11 | 0 | 9 | 0 | 7 | 0 | 16 | 0 | 17 | 2 | 12 | 0 | 12 | 0 | 10 | 0 | 8 | 5 | 14 | 0 | 15 | 5 | 13
INPUTS | 8 | U23/syn2342/U23/syn2342_D2  | \$Net00055_  | &__A__17  | &__A__7/&__A__7_D2  | \$Net00054_  | &__A__16  | &__A__18  | &__A__15
INPUTMC | 8 | 3 | 9 | 2 | 14 | 1 | 2 | 3 | 11 | 2 | 11 | 1 | 8 | 4 | 17 | 1 | 16
EQ | 5 | 
    "&__A__6/&__A__6_D2"  =  "U23/syn2342/U23/syn2342_D2"
	+ "\$Net00054_" * "&__A__16" * /"&__A__18"
	+ /"\$Net00055_" * "&__A__15" * "&__A__17"
	+ /"\$Net00055_" * /"&__A__17" * 
	/"&__A__7/&__A__7_D2"

MACROCELL | 5 | 11 | U31/syn4395/U31/syn4395_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 4 | 0 | 14 | 0 | 13 | 0 | 15 | 5 | 12
INPUTS | 8 | U31/countnum<9>  | &__A__11/&__A__11_D2  | U31/countnum<8>  | &__A__10/&__A__10_D2  | U31/countnum<10>  | U31/countnum<11>  | $OpTx$FX_DC$299  | $OpTx$FX_DC$290.EXP
INPUTMC | 8 | 0 | 7 | 2 | 10 | 0 | 8 | 3 | 16 | 0 | 16 | 0 | 17 | 5 | 0 | 5 | 10
EXPORTS | 1 | 5 | 12
IMPORTS | 1 | 5 | 10
EQ | 18 | 
    "U31/syn4395/U31/syn4395_D2"  =  /"U31/countnum<9>" * "&__A__11/&__A__11_D2"
	+ /"U31/countnum<9>" * /"U31/countnum<8>" * 
	"&__A__10/&__A__10_D2"
	+ /"U31/countnum<8>" * "&__A__11/&__A__11_D2" * 
	"&__A__10/&__A__10_D2"
;Imported pterms FB6_11
	+ /"U31/countnum<9>" * /"U31/countnum<8>" * 
	/"U31/syn3879/U31/syn3879_D2"
	+ /"U31/countnum<9>" * "&__A__10/&__A__10_D2" * 
	/"U31/syn3879/U31/syn3879_D2"
	+ /"U31/countnum<8>" * "&__A__11/&__A__11_D2" * 
	/"U31/syn3879/U31/syn3879_D2"
	+ "&__A__11/&__A__11_D2" * "&__A__10/&__A__10_D2" * 
	/"U31/syn3879/U31/syn3879_D2"
    U31/syn4395/U31/syn4395_D2.EXP  =  "U31/countnum<10>" * "U31/countnum<11>" * 
	"$OpTx$FX_DC$299"
	+ "U31/countnum<11>" * /"&__A__11/&__A__11_D2" * 
	"$OpTx$FX_DC$299"

MACROCELL | 5 | 17 | U31/syn3879/U31/syn3879_D2
ATTRIBUTES | 133888 | 0
OUTPUTMC | 1 | 5 | 10
INPUTS | 9 | U31/countnum<7>  | &__A__9/&__A__9_D2  | U31/countnum<6>  | &__A__8/&__A__8_D2  | $OpTx$FX_DC$
上一页 1 2 3 45
💿 文件大小 1079 K
👤 上传用户 Numb_pqc
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#vhdl #电子琴 #工程 #程序
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