📄 piano.tim
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Performance Summary Report
--------------------------
Design: piano
Device: XC95108-15-PC84
Speed File: Version 3.0
Program: Timing Report Generator: version E.30
Date: Sun Dec 23 16:04:35 2007
Performance Summary:
Clock net '\$Net00059_' path delays:
Clock Pad to Output Pad (tCO) : 108.0ns (6 macrocell levels)
Clock Pad '\$Net00059_' to Output Pad '\$Net00057_' (GCK)
Clock to Setup (tCYC) : 18.0ns (1 macrocell levels)
Clock to Q, net 'U33/countnum.Q' to TFF Setup(D) at '\$Net00068_.D' (GCK)
Target FF drives output net '\$Net00068_'
Minimum Clock Period: 18.0ns
Maximum Internal Clock Speed: 55.5Mhz
(Limited by Cycle Time)
Clock net '\$Net00040_' path delays:
Clock Pad to Output Pad (tCO) : 22.0ns (1 macrocell levels)
Clock Pad '\$Net00040_' to Output Pad '\$Net00037_' (GCK)
Clock to Setup (tCYC) : 18.0ns (1 macrocell levels)
Clock to Q, net 'U1/count.Q' to TFF Setup(D) at '\$Net00001_.D' (GCK)
Target FF drives output net '\$Net00001_'
Minimum Clock Period: 18.0ns
Maximum Internal Clock Speed: 55.5Mhz
(Limited by Cycle Time)
Clock net '\$Net00068_.Q' path delays:
Clock to Setup (tCYC) : 69.0ns (4 macrocell levels)
Clock to Q, net '&__A__14.Q' to DFF Setup(D) at '&__A__18.D' (Pterm Clock)
Target FF drives output net '&__A__18'
Setup to Clock at the Pad (tSU) : 48.0ns (3 macrocell levels)
Data signal '\$Net00061_' to DFF D input Pin at '&__A__18.D'
Clock pad '\$Net00068_.Q' (Pterm Clock)
Minimum Clock Period: 69.0ns
Maximum Internal Clock Speed: 14.4Mhz
(Limited by Cycle Time)
Clock net '\$Net00001_.Q' path delays:
Clock to Setup (tCYC) : 107.0ns (6 macrocell levels)
Clock to Q, net 'U31/countnum<0>.Q' to DFF Setup(D) at 'U31/countnum<0>.D'(Pterm Clock)
Target FF drives output net 'U31/countnum<0>'
Minimum Clock Period: 107.0ns
Maximum Internal Clock Speed: 9.3Mhz
(Limited by Cycle Time)
--------------------------------------------------------------------------------
Clock Pad to Output Pad (tCO) (nsec)
\ From \ \
\ $ $
\ N N
\ e e
\ t t
\ 0 0
\ 0 0
\ 0 0
\ 4 5
\ 0 9
\ _ _
To \------------
\$Net00037_ 22.0
\$Net00044_ 74.0
\$Net00054_ 39.0
\$Net00055_ 40.0
\$Net00057_ 108.0
\$Net00071_ 57.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: \$Net00059_)
\ From U
\ 3
\ 3
\ /
\ c
\ o
\ u
\ n
\ t
\ n
\ u
\ m
\ .
\ Q
To \------
U33/countnum.D 18.0
\$Net00068_.D 18.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: \$Net00040_)
\ From U
\ 1
\ /
\ c
\ o
\ u
\ n
\ t
\ .
\ Q
\
\
\
To \------
U1/count.D 18.0
\$Net00001_.D 18.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: \$Net00068_.Q)
\ From & & & & & U U U U U U
\ _ _ _ _ _ 2 2 2 2 2 2
\ _ _ _ _ _ 0 0 0 0 0 0
\ A A A A A / / / / / /
\ _ _ _ _ _ t t t t t t
\ _ _ _ _ _ i i i i i i
\ 1 1 1 1 1 m m m m m m
\ 4 5 6 7 8 e e e e e e
\ . . . . . < < < < < <
\ Q Q Q Q Q 0 1 2 3 4 5
\ > > > > > >
\ . . . . . .
\ Q Q Q Q Q Q
To \------------------------------------------------------------------
&__A__14.D 37.0 37.0 37.0 37.0 37.0 37.0 20.0
&__A__15.D 36.0 20.0 37.0 37.0 37.0 37.0 37.0 20.0
&__A__16.D 52.0 35.0 19.0 36.0 36.0 36.0 36.0 36.0 20.0
&__A__17.D 53.0 36.0 19.0 20.0 37.0 37.0 37.0 37.0 37.0 19.0
&__A__18.D 69.0 52.0 35.0 35.0 19.0 36.0 36.0 36.0 36.0 36.0 19.0
U20/time<0>.D 18.0
U20/time<1>.D 18.0
U20/time<2>.D 18.0 18.0
U20/time<3>.D 18.0 18.0 18.0
U20/time<4>.D 35.0 35.0 35.0 35.0 35.0
U20/time<5>.D 18.0 18.0 18.0 18.0 18.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: \$Net00001_.Q)
\ From U U U U U U U U U U
\ 3 3 3 3 3 3 3 3 3 3
\ 1 1 1 1 1 1 1 1 1 1
\ / / / / / / / / / /
\ c c c c c c c c c c
\ o o o o o o o o o o
\ u u u u u u u u u u
\ n n n n n n n n n n
\ t t t t t t t t t t
\ n n n n n n n n n n
\ u u u u u u u u u u
\ m m m m m m m m m m
\ < < < < < < < < < <
\ 0 1 1 1 1 2 3 4 5 6
\ > 0 1 2 > > > > > >
\ . > > > . . . . . .
\ Q . . . Q Q Q Q Q Q
\ Q Q Q
To \------------------------------------------------------------
U31/countnum<0>.D 107.0 53.0 53.0 35.0 107.0 107.0 89.0 89.0 106.0 71.0
U31/countnum<10>.D 107.0 53.0 53.0 35.0 107.0 107.0 89.0 89.0 106.0 71.0
U31/countnum<11>.D 107.0 53.0 53.0 35.0 107.0 107.0 89.0 89.0 106.0 71.0
U31/countnum<12>.D 107.0 53.0 53.0 35.0 107.0 107.0 89.0 89.0 106.0 71.0
U31/countnum<1>.D 107.0 53.0 53.0 35.0 107.0 107.0 89.0 89.0 106.0 71.0
U31/countnum<2>.D 107.0 53.0 53.0 35.0 107.0 107.0 89.0 89.0 106.0 71.0
U31/countnum<3>.D 107.0 53.0 53.0 35.0 107.0 107.0 89.0 89.0 106.0 71.0
U31/countnum<4>.D 107.0 53.0 53.0 35.0 107.0 107.0 89.0 89.0 106.0 71.0
U31/countnum<5>.D 107.0 53.0 53.0 35.0 107.0 107.0 89.0 89.0 106.0 71.0
U31/countnum<6>.D 107.0 53.0 53.0 35.0 107.0 107.0 89.0 89.0 106.0 71.0
U31/countnum<7>.D 107.0 53.0 53.0 35.0 107.0 107.0 89.0 89.0 106.0 71.0
U31/countnum<8>.D 107.0 53.0 53.0 35.0 107.0 107.0 89.0 89.0 106.0 71.0
U31/countnum<9>.D 107.0 53.0 53.0 35.0 107.0 107.0 89.0 89.0 106.0 71.0
\$Net00037_.D 91.0 19.0 19.0 19.0 91.0 90.0 73.0 73.0 55.0 55.0
--------------------------------------------------------------------------------
Clock to Setup (tCYC) (nsec)
(Clock: \$Net00001_.Q)
\ From U U U \
\ 3 3 3 $
\ 1 1 1 N
\ / / / e
\ c c c t
\ o o o 0
\ u u u 0
\ n n n 0
\ t t t 3
\ n n n 7
\ u u u _
\ m m m .
\ < < < Q
\ 7 8 9
\ > > >
\ . . .
\ Q Q Q
\
To \------------------------
U31/countnum<0>.D 71.0 88.0 88.0
U31/countnum<10>.D 71.0 88.0 88.0
U31/countnum<11>.D 71.0 88.0 88.0
U31/countnum<12>.D 71.0 88.0 88.0
U31/countnum<1>.D 71.0 88.0 88.0
U31/countnum<2>.D 71.0 88.0 88.0
U31/countnum<3>.D 71.0 88.0 88.0
U31/countnum<4>.D 71.0 88.0 88.0
U31/countnum<5>.D 71.0 88.0 88.0
U31/countnum<6>.D 71.0 88.0 88.0
U31/countnum<7>.D 71.0 88.0 88.0
U31/countnum<8>.D 71.0 88.0 88.0
U31/countnum<9>.D 71.0 88.0 88.0
\$Net00037_.D 72.0 37.0 37.0 19.0
Path Type Definition:
Pad to Pad (tPD) - Reports pad to pad paths that start
at input pads and end at output pads.
Paths are not traced through
registers.
Clock Pad to Output Pad (tCO) - Reports paths that start at input
pads trace through clock inputs of
registers and end at output pads.
Paths are not traced through PRE/CLR
inputs of registers.
Setup to Clock at Pad (tSU) - Reports external setup time of data
to clock at pad. Data path starts at
an input pad and end at register D/T
input. Clock path starts at input pad
and ends at the register clock input.
Paths are not traced through
registers.
Clock to Setup (tCYC) - Register to register cycle time.
Include source register tCO and
destination register tSU.
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