top.vhd

基于spartan3火龙刀系列FPGA开发板制作的VGA实验例程

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is
    Port ( sysclk : in std_logic;
           reset1 : in std_logic;
           ps2clk : inout std_logic;
           ps2data : inout std_logic;
		     hsyncb: buffer std_logic;	-- horizontal (line) sync
		     vsyncb: buffer std_logic;	-- vertical (frame) sync
		     rgb: buffer std_logic_vector(7 downto 0));-- red,green,blue colors));
end top;

architecture Behavioral of top is

signal pblank: std_logic;	-- pipelined video blanking signal

signal clk : std_logic;
signal vgaclk : std_logic;
--signal sysclk_2 : std_logic;--VGA dot clock
--signal div_count : std_logic_vector(1 downto 0);
signal reset : std_logic;

signal hsyn,vsyn : std_logic;
signal hcnt : std_logic_vector(9 downto 0);
signal vcnt : std_logic_vector(9 downto 0);
signal backcolor : std_logic_vector(7 downto 0);


--clock frequence
component count64 
    Port ( sysclk : in std_logic;
           reset : in std_logic;
           clkout : out std_logic);
end component;

--draw background
component frame 
    Port ( clk : in std_logic;
           reset : in std_logic;
           hcnt : in std_logic_vector(9 downto 0);
           vcnt : in std_logic_vector(9 downto 0);
           backcolor : out std_logic_vector(7 downto 0));
end component;

--show the data in CRT
--component vgacore 
--	port
--	(
--		reset : in std_logic;	-- reset
--		clock : in std_logic;	-- VGA dot clock
--		hsyncb : buffer std_logic;	-- horizontal (line) sync
--		vsyncb : buffer std_logic;	-- vertical (frame) sync
--      hcnt : buffer std_logic_vector(9 downto 0);	-- horizontal pixel counter
--      vcnt : buffer std_logic_vector(9 downto 0)	-- vertical line counter
--);
--end component;

component vgasig is
    Port ( clock : in std_logic;
           reset : in std_logic;
           hsyncb : buffer std_logic;
           vsyncb : out std_logic;
           Xaddr : out std_logic_vector(9 downto 0);
           Yaddr : out std_logic_vector(9 downto 0));
end component;

begin
  reset<=not reset1	;
  --made the pixel clock of 25MHz
  divclk: process(reset,sysclk)
  begin
    if reset='0' then
      vgaclk <= '0';
    elsif sysclk'event and sysclk='1' then
      vgaclk <= not vgaclk;
    end if;
  end process;

  F: process(vgaclk,reset)
  begin
	  if reset='0' then
		  pblank <= '0';
	  elsif (vgaclk'event and vgaclk='1') then
	    if (hcnt>639 or vcnt>479) then
	      pblank<='0';
	    else
		   pblank <= '1';
	    end if;
	  end if;
  end process;
  -- composite all the color
  --process (sysclk,reset)
  --begin
   -- if reset='1' then
	 --  rgb <= "00000000";
	 --elsif (sysclk'event and sysclk='1') then
	 --  if pblank='1' then
        rgb <= backcolor ;   --or boardrgb xor ballrgb xor targetrgb;
	--	end if;
	 --end if;
  --end process;

  drawback: frame Port map
         ( clk => vgaclk,
           reset => reset,
           hcnt => hcnt,
           vcnt => vcnt,
           backcolor => backcolor);


  clocknum: count64 Port map
         ( sysclk => vgaclk,
           reset => reset,
           clkout => clk
			  );
 
  

  --showdata: vgacore port map
--	(
--		reset => reset,
--		clock => vgaclk,
--		hsyncb => hsyn,
--		vsyncb => vsyn,
--      hcnt => hcnt,
--		vcnt => vcnt
--   );

	shwodata: vgasig Port map
	      ( clock => vgaclk,
           reset => reset,
           hsyncb => hsyn,
           vsyncb => vsyn,
           Xaddr => hcnt,
           Yaddr => vcnt
			  );

hsyncb <= hsyn;
vsyncb <= vsyn;
 
end Behavioral;