cannon.vhd

基于spartan3火龙刀系列FPGA开发板制作的VGA实验例程

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cannon is
    Port ( clk : in std_logic;
           reset : in std_logic;
			  hcnt : in std_logic_vector(10 downto 0);
			  vcnt : in std_logic_vector(9 downto 0);
           move : in std_logic_vector(9 downto 0);
           cannfire : out std_logic;
           cannonfire : out std_logic_vector(2 downto 0));
end cannon;

architecture Behavioral of cannon is

signal location : std_logic_vector(10 downto 0);
signal cannrgb,firergb : std_logic_vector(2 downto 0);
signal bulletclk : std_logic;

begin

  location <= move;
  

  drawcannon: process(reset,clk,hcnt,vcnt)
  begin
    if reset='1' then
	   cannrgb <= "000";
	 elsif (clk'event and clk='1') then
	   if ((hcnt>(location-5)) and (hcnt<(location+5)) and (vcnt>=550) and (vcnt<=569)) or
		   ((hcnt>(location-10)) and (hcnt<(location+10)) and (vcnt>=570) and (vcnt<=579)) then
			cannrgb <="101";
		 else
		   cannrgb <= "000";
		 end if;
	  end if;
	end process;

	drawbullet: process(

end Behavioral;