count64.vhd

来自「基于spartan3火龙刀系列FPGA开发板制作的VGA实验例程」· VHDL 代码 · 共 27 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity count64 is
    Port ( sysclk : in std_logic;
           reset : in std_logic;
           clkout : out std_logic);
end count64;

architecture Behavioral of count64 is

signal count : std_logic_vector(6 downto 0);

begin
  process (reset,sysclk)
  begin
    if (reset='0') then
      count <= (others=>'0');
    elsif (sysclk'event and sysclk='1') then
      count <= count+'1';
    end if;
  end process;
  clkout <= count(6);
end Behavioral;