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基于spartan3火龙刀系列FPGA开发板制作的7段数码管设计实验例程

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock is
    Port ( seg 	: out std_logic_vector(7 downto 0);
		a 	: out std_logic_vector(3 downto 0);
		en:  out std_logic;
		clk	: in std_logic);
end clock;

architecture Behavioral of clock is
signal divcounter: std_logic_vector(27 downto 0);
signal divclk:std_logic;
signal sec_counter1:std_logic_vector(3 downto 0);
signal sec_counter2:std_logic_vector(3 downto 0);
--signal state:std_logic_vector(1 downto 0);

signal scan	: std_logic_vector(18 downto 0);
signal scan_clk: std_logic_vector(1 downto 0);
signal SecSeg1,SecSeg2	: std_logic_vector(7 downto 0); 

begin
	process(clk)
	begin
		if clk='1' and clk'event then
			if(divcounter>=X"17D783F")then  --17D783F
				divcounter<=X"0000000";
				divclk<=not divclk;
			else
				divcounter<=divcounter+'1';
			end if;
		end if;
	end process;
	
	process(divclk)
	begin
		if divclk'event and divclk='1' then
			if(sec_counter1>=X"9") then	
				sec_counter1<=X"0";
				if(sec_counter2>=X"5")then
					sec_counter2<=X"0";					
				else
					sec_counter2<=sec_counter2+'1';
				end if;
			else
				sec_counter1<=sec_counter1+'1';
			end if;
		end if;
	end process;

	process(clk)
	begin
		if (clk'event and clk='1') then
		scan<=scan+1;
		end if;
	end process;
	scan_clk<=scan(18 downto 17);

	process(scan_clk)
	begin
		case scan_clk is
			when "00"=>
				seg<=SecSeg1;
				a<="0001";
			when "01"=>
				seg<=SecSeg2;
				a<="0010";			
			when others=>seg<="11111111";a<="0000";
		end case;
	end process;

	process(sec_counter1)
	begin
	  case sec_counter1 is
	 when "0000" =>SecSeg1<="00010001";--0
    when "0001" =>SecSeg1<="11010111";--1
    when "0010" =>SecSeg1<="00110010";--2
    when "0011" =>SecSeg1<="10010010";--3
    when "0100" =>SecSeg1<="11010100";--4
    when "0101" =>SecSeg1<="10011000";--5
    when "0110" =>SecSeg1<="00011000";--6
    when "0111" =>SecSeg1<="11010011";--7
    --when "1000" =>SecSeg1<="";--8
    --when "1001" =>SecSeg1<="";--9
	 when others =>SecSeg1<="11111111";
	  end case;
	end process;

	process(sec_counter2)
	begin
	  case sec_counter2 is
	    	when "0000" =>SecSeg2<="00010001";--0
	   	when "0001" =>SecSeg2<="11010111";--1
	    	when "0010" =>SecSeg2<="00110010";--2
	    	when "0011" =>SecSeg2<="10010010";--3
	    	when "0100" =>SecSeg2<="11010100";--4
	    	when "0101" =>SecSeg2<="10011000";--5
		when others =>SecSeg2<="11111111";
	  end case;
	end process;				

  en<='0';

end Behavioral;