uartrec.vhm

PCM数据采集

--
-- Written by Synplicity
-- Product Version "Version 8.8L2"
-- Program "Synplify", Mapper "8.8.0, Build 018R"
-- Thu Jun 19 11:45:55 2008
--

--
-- Written by Synplify version 8.8.0, Build 018R
-- Thu Jun 19 11:45:55 2008
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library xp2;
use xp2.components.all;

entity UartRec is
port(
  Reset :  in std_logic;
  RCLK :  in std_logic;
  UartIn :  in std_logic;
  DataRec : out std_logic_vector(8 downto 0);
  GetData :  out std_logic);
end UartRec;

architecture beh of UartRec is
  signal RSTATE : std_logic_vector(5 downto 0);
  signal RECBUFFER : std_logic_vector(8 downto 0);
  signal RSTATE_3 : std_logic_vector(5 downto 0);
  signal RSTATE_5 : std_logic_vector(0 to 0);
  signal DATAREC_C : std_logic_vector(8 downto 0);
  signal RECBUFFER_QN : std_logic_vector(8 downto 0);
  signal RSTATE_QN : std_logic_vector(5 downto 0);
  signal START : std_logic ;
  signal UN8_RSTATE_0 : std_logic ;
  signal UN13_RSTATE_1 : std_logic ;
  signal UN23_RSTATE_AXBXC1 : std_logic ;
  signal UN23_RSTATE_AXBXC2 : std_logic ;
  signal UN23_RSTATE_AXBXC3 : std_logic ;
  signal UN23_RSTATE_AXBXC4 : std_logic ;
  signal UN23_RSTATE_AXBXC5 : std_logic ;
  signal UN23_RSTATE_P4 : std_logic ;
  signal N_23_I : std_logic ;
  signal UN18_RSTATE_1 : std_logic ;
  signal UN1_RSTATE_2_1 : std_logic ;
  signal UN13_RSTATE_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal RESET_C : std_logic ;
  signal RCLK_C : std_logic ;
  signal UARTIN_C : std_logic ;
  signal GETDATA_C : std_logic ;
  signal GETDATA_QN : std_logic ;
  signal START_QN : std_logic ;
  signal GETDATA_C_I : std_logic ;
  signal UARTIN_C_I : std_logic ;
  signal START_I : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  PUR_INST: PUR port map (
      PUR => VCC);
  VCC_0: VHI port map (
      Z => VCC);
  GND_0: VLO port map (
      Z => GND);
  START_I_Z95: INV port map (
      A => START,
      Z => START_I);
  UARTIN_C_I_Z96: INV port map (
      A => UARTIN_C,
      Z => UARTIN_C_I);
  GETDATA_C_I_Z97: INV port map (
      A => GETDATA_C,
      Z => GETDATA_C_I);
  N_23_I <= (START) or 
	  (UN18_RSTATE_1 and RSTATE(3) and RSTATE(2));
  UN13_RSTATE_1 <= UN13_RSTATE_0 and RSTATE_3(1) and RSTATE(3) and RSTATE(2);
  UN23_RSTATE_AXBXC5 <= (UN23_RSTATE_P4 and RSTATE(4) and not RSTATE(5)) or 
	  (UN23_RSTATE_P4 and START) or 
	  (not RSTATE(4) and not START and RSTATE(5)) or 
	  (not UN23_RSTATE_P4 and not START and RSTATE(5));
  UN23_RSTATE_AXBXC2 <= (RSTATE_3(1) and RSTATE_3(0) and not RSTATE(2)) or 
	  (not RSTATE_3(0) and RSTATE(2) and not START) or 
	  (not RSTATE_3(1) and RSTATE(2) and not START) or 
	  (RSTATE_3(1) and RSTATE_3(0) and START);
  UN23_RSTATE_AXBXC1 <= (RSTATE_3(0) and not RSTATE(1)) or 
	  (not RSTATE_3(0) and RSTATE(1) and not START) or 
	  (RSTATE_3(0) and START);
  UN8_RSTATE_0 <= not RSTATE(1) and RSTATE(0) and not START;
  \DATAREC_0IO[0]_REG\: OFS1P3DX port map (
      D => RECBUFFER(0),
      SP => UN13_RSTATE_1,
      SCLK => RCLK_C,
      CD => GND,
      Q => DATAREC_C(0));
  \DATAREC_0IO[1]_REG\: OFS1P3DX port map (
      D => RECBUFFER(1),
      SP => UN13_RSTATE_1,
      SCLK => RCLK_C,
      CD => GND,
      Q => DATAREC_C(1));
  \DATAREC_0IO[2]_REG\: OFS1P3DX port map (
      D => RECBUFFER(2),
      SP => UN13_RSTATE_1,
      SCLK => RCLK_C,
      CD => GND,
      Q => DATAREC_C(2));
  \DATAREC_0IO[3]_REG\: OFS1P3DX port map (
      D => RECBUFFER(3),
      SP => UN13_RSTATE_1,
      SCLK => RCLK_C,
      CD => GND,
      Q => DATAREC_C(3));
  \DATAREC_0IO[4]_REG\: OFS1P3DX port map (
      D => RECBUFFER(4),
      SP => UN13_RSTATE_1,
      SCLK => RCLK_C,
      CD => GND,
      Q => DATAREC_C(4));
  \DATAREC_0IO[5]_REG\: OFS1P3DX port map (
      D => RECBUFFER(5),
      SP => UN13_RSTATE_1,
      SCLK => RCLK_C,
      CD => GND,
      Q => DATAREC_C(5));
  \DATAREC_0IO[6]_REG\: OFS1P3DX port map (
      D => RECBUFFER(6),
      SP => UN13_RSTATE_1,
      SCLK => RCLK_C,
      CD => GND,
      Q => DATAREC_C(6));
  \DATAREC_0IO[7]_REG\: OFS1P3DX port map (
      D => RECBUFFER(7),
      SP => UN13_RSTATE_1,
      SCLK => RCLK_C,
      CD => GND,
      Q => DATAREC_C(7));
  \DATAREC_0IO[8]_REG\: OFS1P3DX port map (
      D => RECBUFFER(8),
      SP => UN13_RSTATE_1,
      SCLK => RCLK_C,
      CD => GND,
      Q => DATAREC_C(8));
  \RSTATE[0]_REG\: FD1S3AX port map (
      D => RSTATE_5(0),
      CK => RCLK_C,
      Q => RSTATE(0));
  \RSTATE[1]_REG\: FD1S3AX port map (
      D => UN23_RSTATE_AXBXC1,
      CK => RCLK_C,
      Q => RSTATE(1));
  \RSTATE[2]_REG\: FD1S3AX port map (
      D => UN23_RSTATE_AXBXC2,
      CK => RCLK_C,
      Q => RSTATE(2));
  \RSTATE[3]_REG\: FD1S3AX port map (
      D => UN23_RSTATE_AXBXC3,
      CK => RCLK_C,
      Q => RSTATE(3));
  \RSTATE[4]_REG\: FD1S3AX port map (
      D => UN23_RSTATE_AXBXC4,
      CK => RCLK_C,
      Q => RSTATE(4));
  \RSTATE[5]_REG\: FD1S3AX port map (
      D => UN23_RSTATE_AXBXC5,
      CK => RCLK_C,
      Q => RSTATE(5));
  \RECBUFFER[0]_REG\: FD1P3AX port map (
      D => RECBUFFER(1),
      SP => UN8_RSTATE_0,
      CK => RCLK_C,
      Q => RECBUFFER(0));
  \RECBUFFER[1]_REG\: FD1P3AX port map (
      D => RECBUFFER(2),
      SP => UN8_RSTATE_0,
      CK => RCLK_C,
      Q => RECBUFFER(1));
  \RECBUFFER[2]_REG\: FD1P3AX port map (
      D => RECBUFFER(3),
      SP => UN8_RSTATE_0,
      CK => RCLK_C,
      Q => RECBUFFER(2));
  \RECBUFFER[3]_REG\: FD1P3AX port map (
      D => RECBUFFER(4),
      SP => UN8_RSTATE_0,
      CK => RCLK_C,
      Q => RECBUFFER(3));
  \RECBUFFER[4]_REG\: FD1P3AX port map (
      D => RECBUFFER(5),
      SP => UN8_RSTATE_0,
      CK => RCLK_C,
      Q => RECBUFFER(4));
  \RECBUFFER[5]_REG\: FD1P3AX port map (
      D => RECBUFFER(6),
      SP => UN8_RSTATE_0,
      CK => RCLK_C,
      Q => RECBUFFER(5));
  \RECBUFFER[6]_REG\: FD1P3AX port map (
      D => RECBUFFER(7),
      SP => UN8_RSTATE_0,
      CK => RCLK_C,
      Q => RECBUFFER(6));
  \RECBUFFER[7]_REG\: FD1P3AX port map (
      D => RECBUFFER(8),
      SP => UN8_RSTATE_0,
      CK => RCLK_C,
      Q => RECBUFFER(7));
  \RECBUFFER[8]_REG\: FD1P3AX port map (
      D => UARTIN_C,
      SP => UN8_RSTATE_0,
      CK => RCLK_C,
      Q => RECBUFFER(8));
  START_REG: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => VCC,
    CK => UARTIN_C_I,
    CD => GETDATA_C_I,
    Q => START);
  GETDATA_REG: FD1P3AY port map (
      D => START_I,
      SP => N_23_I,
      CK => RCLK_C,
      Q => GETDATA_C);
  GSR_INST: GSR port map (
      GSR => RESET_C);
  GETDATA_PAD: OB port map (
      I => GETDATA_C,
      O => GetData);
  \DATAREC_PAD[8]\: OB port map (
      I => DATAREC_C(8),
      O => DataRec(8));
  \DATAREC_PAD[7]\: OB port map (
      I => DATAREC_C(7),
      O => DataRec(7));
  \DATAREC_PAD[6]\: OB port map (
      I => DATAREC_C(6),
      O => DataRec(6));
  \DATAREC_PAD[5]\: OB port map (
      I => DATAREC_C(5),
      O => DataRec(5));
  \DATAREC_PAD[4]\: OB port map (
      I => DATAREC_C(4),
      O => DataRec(4));
  \DATAREC_PAD[3]\: OB port map (
      I => DATAREC_C(3),
      O => DataRec(3));
  \DATAREC_PAD[2]\: OB port map (
      I => DATAREC_C(2),
      O => DataRec(2));
  \DATAREC_PAD[1]\: OB port map (
      I => DATAREC_C(1),
      O => DataRec(1));
  \DATAREC_PAD[0]\: OB port map (
      I => DATAREC_C(0),
      O => DataRec(0));
  UARTIN_PAD: IB port map (
      I => UartIn,
      O => UARTIN_C);
  RCLK_PAD: IB port map (
      I => RCLK,
      O => RCLK_C);
  RESET_PAD: IB port map (
      I => Reset,
      O => RESET_C);
  UN23_RSTATE_P4 <= not RSTATE_3(3) and RSTATE_3(0) and RSTATE_3(1) and RSTATE_3(2);
  RSTATE_3(1) <= not START and RSTATE(1);
  RSTATE_3(0) <= not START and RSTATE(0);
  RSTATE_3(2) <= not START and RSTATE(2);
  RSTATE_3(5) <= not START and RSTATE(5);
  RSTATE_3(3) <= not START and not RSTATE(3);
  UN23_RSTATE_AXBXC4 <= (START and not UN23_RSTATE_P4) or 
	  (RSTATE(4) and not UN23_RSTATE_P4) or 
	  (not START and not RSTATE(4) and UN23_RSTATE_P4);
  UN18_RSTATE_1 <= RSTATE(0) and RSTATE(1) and RSTATE(4) and RSTATE(5);
  UN1_RSTATE_2_1 <= not RSTATE(1) and not RSTATE(2) and not RSTATE(4);
  UN13_RSTATE_0 <= not RSTATE(0) and RSTATE(4) and RSTATE(5);
  RSTATE_5(0) <= (not RSTATE_3(0) and not UN1_RSTATE_2_1) or 
	  (not RSTATE_3(3) and not RSTATE_3(0)) or 
	  (RSTATE_3(3) and RSTATE_3(0) and not RSTATE_3(5) and UN1_RSTATE_2_1) or 
	  (not RSTATE_3(0) and RSTATE_3(5));
  UN23_RSTATE_AXBXC3 <= (not RSTATE_3(3) and not RSTATE_3(2)) or 
	  (not RSTATE_3(3) and not RSTATE_3(1)) or 
	  (not RSTATE_3(3) and not RSTATE_3(0)) or 
	  (RSTATE_3(3) and RSTATE_3(0) and RSTATE_3(1) and RSTATE_3(2));
  NN_1 <= '0';
  NN_2 <= '1';
end beh;