baudr.vhd.bak

PCM数据采集

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity BaudR is
Port(
	Reset	:in	std_logic;	--low 
	Clock	:in std_logic;  	--32.768Mhz
	CLK_RXD	:buffer std_logic;	--468114Hz
	CLK_TXD	:out std_logic	--117028Hz	
	);

end entity;

architecture ART_BaudR of BaudR is
begin----------------------------------architecture begin
Get_CLK_RXD:
	process(Reset,Clock)
		variable count	:integer range 0 to 34;
	begin
	if Reset = '0' then
		count := 0;
		CLK_RXD <= '0';
	elsif Clock'event and Clock = '1' then
		if count = 34 then --70分频
            count := 0;
			CLK_RXD <= not CLK_RXD;
		else count := count + 1;
		end if;
	end if;
	end process Get_CLK_RXD;
	
Get_CLK_TXD:
	process(Reset,CLK_RXD)
		variable count	:std_logic_vector(1 downto 0);----4分频
	begin
	if Reset = '0' then
		count := "00";
		CLK_TXD <= '0';
	elsif CLK_RXD'event and CLK_RXD = '1' then
		count := count + 1;
		CLK_TXD <= count(1);
	end if;
	end process Get_CLK_TXD;
	
end ART_BaudR;