pcm.log

PCM数据采集

#Build: Synplify for Lattice 9.0L1, Build 024R, Nov 13 2007
#install: D:\ISPTOOLS7_0\SYNPBASE
#OS: Windows XP 5.1
#Hostname: STAR-PANCAT

#Implementation: getpcm

#Wed Jun 18 10:50:57 2008

$ Start of Compile
#Wed Jun 18 10:50:57 2008

Synplicity VHDL Compiler, version 1.0, Build 157R, built Nov 13 2007
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved

@N: CD720 :"D:\ISPTOOLS7_0\SYNPBASE\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"D:\cpld\fpga\getpcm\pcm.vhd":6:7:6:9|Top entity is set to PCM.
VHDL syntax check successful!
@N: CD630 :"D:\cpld\fpga\getpcm\pcm.vhd":6:7:6:9|Synthesizing work.pcm.art_pcm 
@W: CD638 :"D:\cpld\fpga\getpcm\pcm.vhd":24:8:24:13|Signal pclk_8 is undriven 
Post processing for work.pcm.art_pcm
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jun 18 10:50:58 2008

###########################################################]

Total runtime: 00h:00m:01s realtime
Synplicity Generic Technology Mapper, Version 9.0.0, Build 139R, Built Nov 13 2007 20:48:37
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved
Product Version Version 9.0L1
@N: MF249 |Running in 32-bit mode.


RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)
@N: MF179 :|Found 8 bit by 8 bit '==' comparator, 'un17_count'
Automatic dissolve during optimization of view:work.PCM(art_pcm) of un3_count_1(PM_ADDC__0_3_lfxp2_17e)

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Clock Buffers:
  Inserting Clock buffer for port PCLK,	TNM=PCLK


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 51MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		    -5.05ns		  52 /        29
   2		0h:00m:00s		    -5.05ns		  52 /        29
   3		0h:00m:00s		    -5.05ns		  52 /        29
------------------------------------------------------------

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -2.88ns		  65 /        29
Timing driven replication report
No replication required.

   2		0h:00m:01s		    -2.88ns		  65 /        29
   3		0h:00m:01s		    -2.88ns		  65 /        29
   4		0h:00m:01s		    -2.88ns		  65 /        29
------------------------------------------------------------

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		    -2.88ns		  64 /        29
Timing driven replication report
No replication required.

   2		0h:00m:01s		    -2.88ns		  64 /        29
   3		0h:00m:01s		    -2.88ns		  64 /        29
   4		0h:00m:01s		    -2.88ns		  64 /        29
------------------------------------------------------------

Net buffering Report for view:work.PCM(art_pcm):
No nets needed buffering.


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:01s; Memory used current: 51MB peak: 52MB)
@W: BN132 :|Removing instance g0_1_0,  because it is equivalent to instance g0_2
@W: BN132 :|Removing instance g0_1_3,  because it is equivalent to instance g0_0_3
@W: BN132 :|Removing instance un17_count_0.I_24_1_1_0,  because it is equivalent to instance un10_count_a0
Found clock PCM|PCLK with period 5.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Jun 18 10:51:06 2008
#


Top view:               PCM
Requested Frequency:    200.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..


Performance Summary 
*******************


Worst slack in design: -2.948

                   Requested     Estimated     Requested     Estimated                Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group              
----------------------------------------------------------------------------------------------------------------------
PCM|PCLK           200.0 MHz     125.8 MHz     5.000         7.948         -2.948     inferred     Inferred_clkgroup_0
System             200.0 MHz     467.6 MHz     5.000         2.139         2.861      system       default_clkgroup   
======================================================================================================================





Clock Relationships
*******************

Clocks              |    rise  to  rise   |    fall  to  fall    |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------
Starting  Ending    |  constraint  slack  |  constraint  slack   |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------
PCM|PCLK  PCM|PCLK  |  No paths    -      |  5.000       -2.948  |  No paths    -      |  No paths    -    
===========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port             Starting            User           Arrival     Required          
Name             Reference           Constraint     Time        Time         Slack
                 Clock                                                            
----------------------------------------------------------------------------------
DinOrDoutSel     System (rising)     NA             0.000       1.344             
FSYNC            System (rising)     NA             0.000       -2.909            
PCLK             NA                  NA             NA          NA           NA   
PCM_Din          System (rising)     NA             0.000       1.344             
PCM_Dout         System (rising)     NA             0.000       1.344             
Reset            System (rising)     NA             0.000       2.861             
Slot[0]          System (rising)     NA             0.000       -2.663            
Slot[1]          System (rising)     NA             0.000       -2.626            
Slot[2]          System (rising)     NA             0.000       -2.579            
Slot[3]          System (rising)     NA             0.000       -2.504            
Slot[4]          System (rising)     NA             0.000       -1.536            
Slot[5]          System (rising)     NA             0.000       -1.489            
Slot[6]          System (rising)     NA             0.000       -1.292            
Slot[7]          System (rising)     NA             0.000       -0.324            
==================================================================================


Output Ports: 

Port            Starting               User           Arrival     Required          
Name            Reference              Constraint     Time        Time         Slack
                Clock                                                               
------------------------------------------------------------------------------------
Latch           PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[0]     PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[1]     PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[2]     PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[3]     PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[4]     PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[5]     PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[6]     PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[7]     PCM|PCLK (falling)     NA             4.187       5.000             
====================================================================================


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report
Part: lfxp2_17e-5

Register bits: 29 of 16560 (0%)
I/O cells:       23

Details:
CCU2B:          3
FD1P3AX:        8
FD1S3AX:        12
GSR:            1
IB:             14
INV:            1
OB:             9
OFS1P3DX:       9
ORCALUT4:       59
VHI:            1
VLO:            1

Finished restoring hierarchy (Time elapsed 0h:00m:01s; Memory used current: 51MB peak: 52MB)
Writing Analyst data base D:\cpld\fpga\getpcm\PCM.srm
@N: MF203 |Set autoconstraint_io 
Writing EDIF Netlist and constraint files
@N: MF203 |Set autoconstraint_io 
Version 9.0L1
Writing Verilog Simulation files
@N: MF203 |Set autoconstraint_io 
Writing VHDL Simulation files
@N: MF203 |Set autoconstraint_io 
@N: MF203 |Set autoconstraint_io 
Mapper successful!
Process took 0h:00m:08s realtime, 0h:00m:02s cputime
# Wed Jun 18 10:51:07 2008

###########################################################]

Total runtime: 00h:00m:10s realtime