📄 uartsend.log
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Busy UartSend|SendClk (rising) NA 5.240 5.000
UartOut UartSend|SendClk (rising) NA 4.187 5.000
=======================================================================================
##### END OF TIMING REPORT #####]
---------------------------------------
Resource Usage Report
Part: lfxp2_17e-5
Register bits: 27 of 16560 (0%)
I/O cells: 13
Details:
FD1P3DX: 1
FD1S3AX: 3
FD1S3BX: 11
FD1S3DX: 10
FD1S3JX: 1
GSR: 1
IB: 11
INV: 1
OB: 2
OFS1P3BX: 1
ORCALUT4: 57
PFUMX: 7
VHI: 1
VLO: 1
Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)
Writing Analyst data base D:\cpld\fpga\getpcm\UartSend.srm
@N: MF203 |Set autoconstraint_io
Warning: Found 11 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_24.t2
1) instance work.UartSend(art_uartsend)-I_24.lat_r, output net "I_24.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_1" in work.UartSend(art_uartsend)
net "Reset_c" in work.UartSend(art_uartsend)
net "un1_latch" in work.UartSend(art_uartsend)
net "GND" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net un1_latch
2) instance work.UartSend(art_uartsend)-un1_latch, output net "un1_latch" in work.UartSend(art_uartsend)
input nets to instance:
net "Latch_c" in work.UartSend(art_uartsend)
net "N_1" in work.UartSend(art_uartsend)
net "SendComp.Q.o1" in work.UartSend(art_uartsend)
net "SendComp.Q.o2" in work.UartSend(art_uartsend)
@W: BN137 :|Found combinational loop during mapping at net I_15.t2
3) instance work.UartSend(art_uartsend)-I_15.lat_r, output net "I_15.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "Reset_c" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "N_3" in work.UartSend(art_uartsend)
net "GND" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_23.t2
4) instance work.UartSend(art_uartsend)-I_23.lat_r, output net "I_23.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_4" in work.UartSend(art_uartsend)
net "N_11_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[0]" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_17.t2
5) instance work.UartSend(art_uartsend)-I_17.lat_r, output net "I_17.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_5" in work.UartSend(art_uartsend)
net "N_17_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[6]" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_16.t2
6) instance work.UartSend(art_uartsend)-I_16.lat_r, output net "I_16.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_6" in work.UartSend(art_uartsend)
net "N_18_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[7]" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_18.t2
7) instance work.UartSend(art_uartsend)-I_18.lat_r, output net "I_18.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_7" in work.UartSend(art_uartsend)
net "N_16_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[5]" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_19.t2
8) instance work.UartSend(art_uartsend)-I_19.lat_r, output net "I_19.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_8" in work.UartSend(art_uartsend)
net "N_15_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[4]" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_20.t2
9) instance work.UartSend(art_uartsend)-I_20.lat_r, output net "I_20.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_9" in work.UartSend(art_uartsend)
net "N_14_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[3]" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_21.t2
10) instance work.UartSend(art_uartsend)-I_21.lat_r, output net "I_21.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_10" in work.UartSend(art_uartsend)
net "N_13_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[2]" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_22.t2
11) instance work.UartSend(art_uartsend)-I_22.lat_r, output net "I_22.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_11" in work.UartSend(art_uartsend)
net "N_12_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[1]" in work.UartSend(art_uartsend)
End of loops
Writing EDIF Netlist and constraint files
@N: MF203 |Set autoconstraint_io
Warning: Found 11 combinational loops!
Each loop is reported with an instance in the loop
and nets connected to that instance.
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_24.t2
1) instance work.UartSend(art_uartsend)-I_24.lat_r, output net "I_24.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_1" in work.UartSend(art_uartsend)
net "Reset_c" in work.UartSend(art_uartsend)
net "un1_latch" in work.UartSend(art_uartsend)
net "GND" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net un1_latch
2) instance work.UartSend(art_uartsend)-un1_latch, output net "un1_latch" in work.UartSend(art_uartsend)
input nets to instance:
net "Latch_c" in work.UartSend(art_uartsend)
net "N_1" in work.UartSend(art_uartsend)
net "SendComp.Q.o1" in work.UartSend(art_uartsend)
net "SendComp.Q.o2" in work.UartSend(art_uartsend)
@W: BN137 :|Found combinational loop during mapping at net I_15.t2
3) instance work.UartSend(art_uartsend)-I_15.lat_r, output net "I_15.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "Reset_c" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "N_3" in work.UartSend(art_uartsend)
net "GND" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_23.t2
4) instance work.UartSend(art_uartsend)-I_23.lat_r, output net "I_23.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_4" in work.UartSend(art_uartsend)
net "N_11_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[0]" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_17.t2
5) instance work.UartSend(art_uartsend)-I_17.lat_r, output net "I_17.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_5" in work.UartSend(art_uartsend)
net "N_17_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[6]" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_16.t2
6) instance work.UartSend(art_uartsend)-I_16.lat_r, output net "I_16.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_6" in work.UartSend(art_uartsend)
net "N_18_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[7]" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_18.t2
7) instance work.UartSend(art_uartsend)-I_18.lat_r, output net "I_18.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_7" in work.UartSend(art_uartsend)
net "N_16_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[5]" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_19.t2
8) instance work.UartSend(art_uartsend)-I_19.lat_r, output net "I_19.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_8" in work.UartSend(art_uartsend)
net "N_15_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[4]" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_20.t2
9) instance work.UartSend(art_uartsend)-I_20.lat_r, output net "I_20.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_9" in work.UartSend(art_uartsend)
net "N_14_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[3]" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_21.t2
10) instance work.UartSend(art_uartsend)-I_21.lat_r, output net "I_21.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_10" in work.UartSend(art_uartsend)
net "N_13_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[2]" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Found combinational loop during mapping at net I_22.t2
11) instance work.UartSend(art_uartsend)-I_22.lat_r, output net "I_22.t2" in work.UartSend(art_uartsend)
input nets to instance:
net "N_11" in work.UartSend(art_uartsend)
net "N_12_i" in work.UartSend(art_uartsend)
net "N_2" in work.UartSend(art_uartsend)
net "Data_c[1]" in work.UartSend(art_uartsend)
End of loops
Version 9.0L1
Writing Verilog Simulation files
@N: MF203 |Set autoconstraint_io
Writing VHDL Simulation files
@N: MF203 |Set autoconstraint_io
@N: MF203 |Set autoconstraint_io
Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jun 18 11:01:45 2008
###########################################################]
Total runtime: 00h:00m:02s realtime
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