uartsend.log

PCM数据采集

#Build: Synplify for Lattice 9.0L1, Build 024R, Nov 13 2007
#install: D:\ISPTOOLS7_0\SYNPBASE
#OS: Windows XP 5.1
#Hostname: STAR-PANCAT

#Implementation: getpcm

#Wed Jun 18 11:01:43 2008

$ Start of Compile
#Wed Jun 18 11:01:43 2008

Synplicity VHDL Compiler, version 1.0, Build 157R, built Nov 13 2007
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved

@N: CD720 :"D:\ISPTOOLS7_0\SYNPBASE\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"D:\cpld\fpga\getpcm\uartsend.vhd":6:7:6:14|Top entity is set to UartSend.
VHDL syntax check successful!
@N: CD630 :"D:\cpld\fpga\getpcm\uartsend.vhd":6:7:6:14|Synthesizing work.uartsend.art_uartsend 
@W: CG296 :"D:\cpld\fpga\getpcm\uartsend.vhd":22:0:22:6|Incomplete sensitivity list - assuming completeness
@W: CG290 :"D:\cpld\fpga\getpcm\uartsend.vhd":32:19:32:22|Referenced variable data is not in sensitivity list
Post processing for work.uartsend.art_uartsend
@W: CL113 :"D:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Feedback mux created for signal UartOut.
@W: CL113 :"D:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Feedback mux created for signal SendComp.
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jun 18 11:01:43 2008

###########################################################]

Total runtime: 00h:00m:00s realtime
Synplicity Generic Technology Mapper, Version 9.0.0, Build 139R, Built Nov 13 2007 20:48:37
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved
Product Version Version 9.0L1
@N: MF249 |Running in 32-bit mode.


RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Clock Buffers:
  Inserting Clock buffer for port SendClk,	TNM=SendClk


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 51MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 51MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 51MB)

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		     0.56ns		  29 /        15
   2		0h:00m:00s		     0.77ns		  28 /        15
   3		0h:00m:00s		     0.77ns		  28 /        15
   4		0h:00m:00s		     0.77ns		  28 /        15
------------------------------------------------------------

Net buffering Report for view:work.UartSend(art_uartsend):
No nets needed buffering.


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)
@W: BN132 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Removing sequential instance tstate_2_.Q.res_lat,  because it is equivalent to instance tstate_1_.Q.res_lat
@W: BN132 :"d:\cpld\fpga\getpcm\uartsend.vhd":26:4:26:5|Removing sequential instance tstate_0_.Q.res_lat,  because it is equivalent to instance tstate_1_.Q.res_lat
Warning: Found 11 combinational loops!
         Each loop is reported with an instance in the loop
         and nets connected to that instance.
@W: BN137 :|Found combinational loop during mapping at net I_15.t2
1) instance work.UartSend(art_uartsend)-I_15.lat_r, output net "I_15.t2" in work.UartSend(art_uartsend)
    input nets to instance:
	net "Reset_c" in work.UartSend(art_uartsend)
	net "I_15.t1" in work.UartSend(art_uartsend)
@W: BN137 :"d:\cpld\fpga\getpcm\uartsend.vhd":31:10:31:38|Found combinational loop during mapping at net un1_latch
2) instance work.UartSend(art_uartsend)-un1_latch, output net "un1_latch" in work.UartSend(art_uartsend)
    input nets to instance:
	net "Latch_c" in work.UartSend(art_uartsend)
	net "Busy_c" in work.UartSend(art_uartsend)
	net "GND" in work.UartSend(art_uartsend)
	net "GND" in work.UartSend(art_uartsend)
@W: BN137 :|Found combinational loop during mapping at net I_24.t2
3) instance work.UartSend(art_uartsend)-I_24.lat_r, output net "I_24.t2" in work.UartSend(art_uartsend)
    input nets to instance:
	net "I_24.un1" in work.UartSend(art_uartsend)
	net "I_24.t1" in work.UartSend(art_uartsend)
@W: BN137 :|Found combinational loop during mapping at net I_23.t2
4) instance work.UartSend(art_uartsend)-I_23.lat_r, output net "I_23.t2" in work.UartSend(art_uartsend)
    input nets to instance:
	net "I_23.un1" in work.UartSend(art_uartsend)
	net "I_23.t1" in work.UartSend(art_uartsend)
@W: BN137 :|Found combinational loop during mapping at net I_22.t2
5) instance work.UartSend(art_uartsend)-I_22.lat_r, output net "I_22.t2" in work.UartSend(art_uartsend)
    input nets to instance:
	net "I_22.un1" in work.UartSend(art_uartsend)
	net "I_22.t1" in work.UartSend(art_uartsend)
@W: BN137 :|Found combinational loop during mapping at net I_21.t2
6) instance work.UartSend(art_uartsend)-I_21.lat_r, output net "I_21.t2" in work.UartSend(art_uartsend)
    input nets to instance:
	net "I_21.un1" in work.UartSend(art_uartsend)
	net "I_21.t1" in work.UartSend(art_uartsend)
@W: BN137 :|Found combinational loop during mapping at net I_20.t2
7) instance work.UartSend(art_uartsend)-I_20.lat_r, output net "I_20.t2" in work.UartSend(art_uartsend)
    input nets to instance:
	net "I_20.un1" in work.UartSend(art_uartsend)
	net "I_20.t1" in work.UartSend(art_uartsend)
@W: BN137 :|Found combinational loop during mapping at net I_19.t2
8) instance work.UartSend(art_uartsend)-I_19.lat_r, output net "I_19.t2" in work.UartSend(art_uartsend)
    input nets to instance:
	net "I_19.un1" in work.UartSend(art_uartsend)
	net "I_19.t1" in work.UartSend(art_uartsend)
@W: BN137 :|Found combinational loop during mapping at net I_18.t2
9) instance work.UartSend(art_uartsend)-I_18.lat_r, output net "I_18.t2" in work.UartSend(art_uartsend)
    input nets to instance:
	net "I_18.un1" in work.UartSend(art_uartsend)
	net "I_18.t1" in work.UartSend(art_uartsend)
@W: BN137 :|Found combinational loop during mapping at net I_17.t2
10) instance work.UartSend(art_uartsend)-I_17.lat_r, output net "I_17.t2" in work.UartSend(art_uartsend)
    input nets to instance:
	net "I_17.un1" in work.UartSend(art_uartsend)
	net "I_17.t1" in work.UartSend(art_uartsend)
@W: BN137 :|Found combinational loop during mapping at net I_16.t2
11) instance work.UartSend(art_uartsend)-I_16.lat_r, output net "I_16.t2" in work.UartSend(art_uartsend)
    input nets to instance:
	net "I_16.un1" in work.UartSend(art_uartsend)
	net "I_16.t1" in work.UartSend(art_uartsend)
End of loops
Found clock UartSend|SendClk with period 5.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Jun 18 11:01:44 2008
#


Top view:               UartSend
Requested Frequency:    200.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..


Performance Summary 
*******************


Worst slack in design: -0.240

                     Requested     Estimated     Requested     Estimated                Clock        Clock              
Starting Clock       Frequency     Frequency     Period        Period        Slack      Type         Group              
------------------------------------------------------------------------------------------------------------------------
UartSend|SendClk     200.0 MHz     190.8 MHz     5.000         5.240         -0.240     inferred     Inferred_clkgroup_0
System               200.0 MHz     478.7 MHz     5.000         2.089         2.911      system       default_clkgroup   
========================================================================================================================





Clock Relationships
*******************

Clocks                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------
Starting          Ending            |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------
UartSend|SendClk  UartSend|SendClk  |  5.000       -0.240  |  No paths    -      |  No paths    -      |  No paths    -    
===========================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port        Starting            User           Arrival     Required          
Name        Reference           Constraint     Time        Time         Slack
            Clock                                                            
-----------------------------------------------------------------------------
Data[0]     NA                  NA             NA          NA           NA   
Data[1]     NA                  NA             NA          NA           NA   
Data[2]     NA                  NA             NA          NA           NA   
Data[3]     NA                  NA             NA          NA           NA   
Data[4]     NA                  NA             NA          NA           NA   
Data[5]     NA                  NA             NA          NA           NA   
Data[6]     NA                  NA             NA          NA           NA   
Data[7]     NA                  NA             NA          NA           NA   
Latch       NA                  NA             NA          NA           NA   
Reset       System (rising)     NA             0.000       2.911             
SendClk     NA                  NA             NA          NA           NA   
=============================================================================


Output Ports: 

Port        Starting                      User           Arrival     Required          
Name        Reference                     Constraint     Time        Time         Slack
            Clock