uartrec.vm

PCM数据采集

//
// Written by Synplify
// Product Version "Version 8.8L2"
// Program "Synplify", Mapper "8.8.0, Build 018R"
// Thu Jun 19 11:45:55 2008
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\isptools7_0\synpbase\lib\vhd\std.vhd "
// file 2 "\d:\isptools7_0\ispcpld\..\cae_library\synthesis\vhdl\xp2.vhd "
// file 3 "\d:\isptools7_0\synpbase\lib\vhd\std1164.vhd "
// file 4 "\d:\cpld\fpga\getpcm\uartrec.vhd "
// file 5 "\d:\isptools7_0\synpbase\lib\vhd\arith.vhd "
// file 6 "\d:\isptools7_0\synpbase\lib\vhd\unsigned.vhd "

`timescale 100 ps/100 ps
module UartRec (
  Reset,
  RCLK,
  UartIn,
  DataRec,
  GetData
)
;
input Reset ;
input RCLK ;
input UartIn ;
output [8:0] DataRec ;
output GetData ;
wire Reset ;
wire RCLK ;
wire UartIn ;
wire GetData ;
wire [5:0] rstate;
wire [8:0] recbuffer;
wire [5:0] rstate_3;
wire [0:0] rstate_5;
wire [8:0] DataRec_c;
wire [8:0] recbuffer_QN;
wire [5:0] rstate_QN;
wire Start ;
wire un8_rstate_0 ;
wire un13_rstate_1 ;
wire un23_rstate_axbxc1 ;
wire un23_rstate_axbxc2 ;
wire un23_rstate_axbxc3 ;
wire un23_rstate_axbxc4 ;
wire un23_rstate_axbxc5 ;
wire un23_rstate_p4 ;
wire N_23_i ;
wire un18_rstate_1 ;
wire un1_rstate_2_1 ;
wire un13_rstate_0 ;
wire GND ;
wire VCC ;
wire Reset_c ;
wire RCLK_c ;
wire UartIn_c ;
wire GetData_c ;
wire GetData_QN ;
wire Start_QN ;
wire GetData_c_i ;
wire UartIn_c_i ;
wire Start_i ;
wire GND_Z ;
wire VCC_Z ;
  PUR PUR_INST (
	.PUR(VCC)
);
  VHI VCC_0 (
	.Z(VCC)
);
  VLO GND_0 (
	.Z(GND)
);
  INV Start_i_cZ (
	.A(Start),
	.Z(Start_i)
);
  INV UartIn_c_i_cZ (
	.A(UartIn_c),
	.Z(UartIn_c_i)
);
  INV GetData_c_i_cZ (
	.A(GetData_c),
	.Z(GetData_c_i)
);
assign N_23_i = (Start) | (Start & ~rstate[2]) | (Start & rstate[2]) | 
   (Start & ~rstate[3] & rstate[2]) | (un18_rstate_1 & rstate[3] & rstate[2]) | 
   (un18_rstate_1 & ~Start & rstate[3] & rstate[2]) | (Start & rstate[3] & 
   rstate[2]);
assign un13_rstate_1 = (un13_rstate_0 & rstate_3[1] & rstate[3] & rstate[2]);
assign un23_rstate_axbxc5 = (un23_rstate_p4 & Start) | (un23_rstate_p4 & 
   rstate[4] & ~rstate[5]) | (un23_rstate_p4 & rstate[4] & ~Start & ~rstate[5]) | 
   (un23_rstate_p4 & Start & ~rstate[5]) | (un23_rstate_p4 & ~rstate[4] & 
   rstate[5]) | (~un23_rstate_p4 & ~Start & rstate[5]) | (~rstate[4] & 
   ~Start & rstate[5]) | (~un23_rstate_p4 & rstate[4] & ~Start & rstate[5]) | 
   (un23_rstate_p4 & Start & rstate[5]);
assign un23_rstate_axbxc2 = (rstate_3[1] & rstate_3[0] & ~rstate[2]) | 
   (rstate_3[1] & rstate_3[0] & ~rstate[2] & ~Start) | (~rstate_3[1] & 
   rstate[2] & ~Start) | (~rstate_3[0] & rstate[2] & ~Start) | (~rstate_3[1] & 
   rstate_3[0] & rstate[2] & ~Start) | (rstate_3[1] & rstate_3[0] & Start);
assign un23_rstate_axbxc1 = (rstate_3[0] & ~rstate[1]) | (rstate_3[0] & 
   ~rstate[1] & ~Start) | (~rstate_3[0] & rstate[1] & ~Start) | (rstate_3[0] & 
   Start);
assign un8_rstate_0 = (~rstate[1] & rstate[0] & ~Start);
// @4:39
  OFS1P3DX \DataRec_0io_Z[0]  (
	.D(recbuffer[0]),
	.SP(un13_rstate_1),
	.SCLK(RCLK_c),
	.CD(GND),
	.Q(DataRec_c[0])
);
// @4:39
  OFS1P3DX \DataRec_0io_Z[1]  (
	.D(recbuffer[1]),
	.SP(un13_rstate_1),
	.SCLK(RCLK_c),
	.CD(GND),
	.Q(DataRec_c[1])
);
// @4:39
  OFS1P3DX \DataRec_0io_Z[2]  (
	.D(recbuffer[2]),
	.SP(un13_rstate_1),
	.SCLK(RCLK_c),
	.CD(GND),
	.Q(DataRec_c[2])
);
// @4:39
  OFS1P3DX \DataRec_0io_Z[3]  (
	.D(recbuffer[3]),
	.SP(un13_rstate_1),
	.SCLK(RCLK_c),
	.CD(GND),
	.Q(DataRec_c[3])
);
// @4:39
  OFS1P3DX \DataRec_0io_Z[4]  (
	.D(recbuffer[4]),
	.SP(un13_rstate_1),
	.SCLK(RCLK_c),
	.CD(GND),
	.Q(DataRec_c[4])
);
// @4:39
  OFS1P3DX \DataRec_0io_Z[5]  (
	.D(recbuffer[5]),
	.SP(un13_rstate_1),
	.SCLK(RCLK_c),
	.CD(GND),
	.Q(DataRec_c[5])
);
// @4:39
  OFS1P3DX \DataRec_0io_Z[6]  (
	.D(recbuffer[6]),
	.SP(un13_rstate_1),
	.SCLK(RCLK_c),
	.CD(GND),
	.Q(DataRec_c[6])
);
// @4:39
  OFS1P3DX \DataRec_0io_Z[7]  (
	.D(recbuffer[7]),
	.SP(un13_rstate_1),
	.SCLK(RCLK_c),
	.CD(GND),
	.Q(DataRec_c[7])
);
// @4:39
  OFS1P3DX \DataRec_0io_Z[8]  (
	.D(recbuffer[8]),
	.SP(un13_rstate_1),
	.SCLK(RCLK_c),
	.CD(GND),
	.Q(DataRec_c[8])
);
// @4:39
  FD1S3AX \rstate_Z[0]  (
	.D(rstate_5[0]),
	.CK(RCLK_c),
	.Q(rstate[0])
);
// @4:39
  FD1S3AX \rstate_Z[1]  (
	.D(un23_rstate_axbxc1),
	.CK(RCLK_c),
	.Q(rstate[1])
);
// @4:39
  FD1S3AX \rstate_Z[2]  (
	.D(un23_rstate_axbxc2),
	.CK(RCLK_c),
	.Q(rstate[2])
);
// @4:39
  FD1S3AX \rstate_Z[3]  (
	.D(un23_rstate_axbxc3),
	.CK(RCLK_c),
	.Q(rstate[3])
);
// @4:39
  FD1S3AX \rstate_Z[4]  (
	.D(un23_rstate_axbxc4),
	.CK(RCLK_c),
	.Q(rstate[4])
);
// @4:39
  FD1S3AX \rstate_Z[5]  (
	.D(un23_rstate_axbxc5),
	.CK(RCLK_c),
	.Q(rstate[5])
);
// @4:39
  FD1P3AX \recbuffer_Z[0]  (
	.D(recbuffer[1]),
	.SP(un8_rstate_0),
	.CK(RCLK_c),
	.Q(recbuffer[0])
);
// @4:39
  FD1P3AX \recbuffer_Z[1]  (
	.D(recbuffer[2]),
	.SP(un8_rstate_0),
	.CK(RCLK_c),
	.Q(recbuffer[1])
);
// @4:39
  FD1P3AX \recbuffer_Z[2]  (
	.D(recbuffer[3]),
	.SP(un8_rstate_0),
	.CK(RCLK_c),
	.Q(recbuffer[2])
);
// @4:39
  FD1P3AX \recbuffer_Z[3]  (
	.D(recbuffer[4]),
	.SP(un8_rstate_0),
	.CK(RCLK_c),
	.Q(recbuffer[3])
);
// @4:39
  FD1P3AX \recbuffer_Z[4]  (
	.D(recbuffer[5]),
	.SP(un8_rstate_0),
	.CK(RCLK_c),
	.Q(recbuffer[4])
);
// @4:39
  FD1P3AX \recbuffer_Z[5]  (
	.D(recbuffer[6]),
	.SP(un8_rstate_0),
	.CK(RCLK_c),
	.Q(recbuffer[5])
);
// @4:39
  FD1P3AX \recbuffer_Z[6]  (
	.D(recbuffer[7]),
	.SP(un8_rstate_0),
	.CK(RCLK_c),
	.Q(recbuffer[6])
);
// @4:39
  FD1P3AX \recbuffer_Z[7]  (
	.D(recbuffer[8]),
	.SP(un8_rstate_0),
	.CK(RCLK_c),
	.Q(recbuffer[7])
);
// @4:39
  FD1P3AX \recbuffer_Z[8]  (
	.D(UartIn_c),
	.SP(un8_rstate_0),
	.CK(RCLK_c),
	.Q(recbuffer[8])
);
// @4:28
  FD1S3DX Start_Z (
	.D(VCC),
	.CK(UartIn_c_i),
	.CD(GetData_c_i),
	.Q(Start)
);
defparam Start_Z.GSR="DISABLED";
// @4:39
  FD1P3AY GetData_Z (
	.D(Start_i),
	.SP(N_23_i),
	.CK(RCLK_c),
	.Q(GetData_c)
);
  GSR GSR_INST (
	.GSR(Reset_c)
);
// @4:12
  OB GetData_pad (
	.I(GetData_c),
	.O(GetData)
);
// @4:11
  OB \DataRec_pad[8]  (
	.I(DataRec_c[8]),
	.O(DataRec[8])
);
// @4:11
  OB \DataRec_pad[7]  (
	.I(DataRec_c[7]),
	.O(DataRec[7])
);
// @4:11
  OB \DataRec_pad[6]  (
	.I(DataRec_c[6]),
	.O(DataRec[6])
);
// @4:11
  OB \DataRec_pad[5]  (
	.I(DataRec_c[5]),
	.O(DataRec[5])
);
// @4:11
  OB \DataRec_pad[4]  (
	.I(DataRec_c[4]),
	.O(DataRec[4])
);
// @4:11
  OB \DataRec_pad[3]  (
	.I(DataRec_c[3]),
	.O(DataRec[3])
);
// @4:11
  OB \DataRec_pad[2]  (
	.I(DataRec_c[2]),
	.O(DataRec[2])
);
// @4:11
  OB \DataRec_pad[1]  (
	.I(DataRec_c[1]),
	.O(DataRec[1])
);
// @4:11
  OB \DataRec_pad[0]  (
	.I(DataRec_c[0]),
	.O(DataRec[0])
);
// @4:10
  IB UartIn_pad (
	.I(UartIn),
	.O(UartIn_c)
);
// @4:9
  IB RCLK_pad (
	.I(RCLK),
	.O(RCLK_c)
);
// @4:8
  IB Reset_pad (
	.I(Reset),
	.O(Reset_c)
);
assign un23_rstate_p4 = (~rstate_3[3] & rstate_3[0] & rstate_3[1] & rstate_3[2]);
assign rstate_3[1] = (~Start & rstate[1]);
assign rstate_3[0] = (~Start & rstate[0]);
assign rstate_3[2] = (~Start & rstate[2]);
assign rstate_3[5] = (~Start & rstate[5]);
assign rstate_3[3] = (~Start & ~rstate[3]);
assign un23_rstate_axbxc4 = (Start & ~un23_rstate_p4) | (Start & ~rstate[4] & 
   ~un23_rstate_p4) | (rstate[4] & ~un23_rstate_p4) | (~Start & ~rstate[4] & 
   un23_rstate_p4);
assign un18_rstate_1 = (rstate[0] & rstate[1] & rstate[4] & rstate[5]);
assign un1_rstate_2_1 = (~rstate[1] & ~rstate[2] & ~rstate[4]);
assign un13_rstate_0 = (~rstate[0] & rstate[4] & rstate[5]);
assign rstate_5[0] = (~rstate_3[3] & ~rstate_3[0]) | (~rstate_3[3] & ~rstate_3[0] & 
   ~rstate_3[5]) | (~rstate_3[0] & rstate_3[5]) | (~rstate_3[0] & ~un1_rstate_2_1) | 
   (~rstate_3[3] & ~rstate_3[0] & un1_rstate_2_1) | (~rstate_3[3] & ~rstate_3[0] & 
   ~rstate_3[5] & un1_rstate_2_1) | (rstate_3[3] & rstate_3[0] & ~rstate_3[5] & 
   un1_rstate_2_1) | (~rstate_3[0] & rstate_3[5] & un1_rstate_2_1);
assign un23_rstate_axbxc3 = (~rstate_3[3] & ~rstate_3[0]) | (~rstate_3[3] & 
   ~rstate_3[1]) | (~rstate_3[3] & ~rstate_3[0] & rstate_3[1]) | (~rstate_3[3] & 
   ~rstate_3[2]) | (~rstate_3[3] & ~rstate_3[0] & rstate_3[2]) | (~rstate_3[3] & 
   ~rstate_3[1] & rstate_3[2]) | (~rstate_3[3] & ~rstate_3[0] & rstate_3[1] & 
   rstate_3[2]) | (rstate_3[3] & rstate_3[0] & rstate_3[1] & rstate_3[2]);
  assign GND_Z = 1'b0;
  assign VCC_Z = 1'b1;
endmodule /* UartRec */