fifo_dc.vhd

PCM数据采集

-- VHDL netlist generated by SCUBA ispLever_v70_SP2_Build (24)
-- Module  Version: 4.3
--D:\ispTOOLS7_0\ispfpga\bin\nt\scuba.exe -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch mg5a00 -type ebfifo -depth 512 -width 9 -depth 512 -no_enable -pe -1 -pf -1 -e 

-- Wed Jun 18 17:17:15 2008

library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library xp2;
use xp2.components.all;
-- synopsys translate_on

entity FIFO_DC is
    port (
        Data: in  std_logic_vector(8 downto 0); 
        WrClock: in  std_logic; 
        RdClock: in  std_logic; 
        WrEn: in  std_logic; 
        RdEn: in  std_logic; 
        Reset: in  std_logic; 
        RPReset: in  std_logic; 
        Q: out  std_logic_vector(8 downto 0); 
        Empty: out  std_logic; 
        Full: out  std_logic);
end FIFO_DC;

architecture Structure of FIFO_DC is

    -- internal signal declarations
    signal invout_1: std_logic;
    signal invout_0: std_logic;
    signal w_g2b_xor_cluster_1: std_logic;
    signal r_g2b_xor_cluster_1: std_logic;
    signal w_gdata_0: std_logic;
    signal w_gdata_1: std_logic;
    signal w_gdata_2: std_logic;
    signal w_gdata_3: std_logic;
    signal w_gdata_4: std_logic;
    signal w_gdata_5: std_logic;
    signal w_gdata_6: std_logic;
    signal w_gdata_7: std_logic;
    signal w_gdata_8: std_logic;
    signal wptr_0: std_logic;
    signal wptr_1: std_logic;
    signal wptr_2: std_logic;
    signal wptr_3: std_logic;
    signal wptr_4: std_logic;
    signal wptr_5: std_logic;
    signal wptr_6: std_logic;
    signal wptr_7: std_logic;
    signal wptr_8: std_logic;
    signal wptr_9: std_logic;
    signal r_gdata_0: std_logic;
    signal r_gdata_1: std_logic;
    signal r_gdata_2: std_logic;
    signal r_gdata_3: std_logic;
    signal r_gdata_4: std_logic;
    signal r_gdata_5: std_logic;
    signal r_gdata_6: std_logic;
    signal r_gdata_7: std_logic;
    signal r_gdata_8: std_logic;
    signal rptr_0: std_logic;
    signal rptr_1: std_logic;
    signal rptr_2: std_logic;
    signal rptr_3: std_logic;
    signal rptr_4: std_logic;
    signal rptr_5: std_logic;
    signal rptr_6: std_logic;
    signal rptr_7: std_logic;
    signal rptr_8: std_logic;
    signal rptr_9: std_logic;
    signal w_gcount_0: std_logic;
    signal w_gcount_1: std_logic;
    signal w_gcount_2: std_logic;
    signal w_gcount_3: std_logic;
    signal w_gcount_4: std_logic;
    signal w_gcount_5: std_logic;
    signal w_gcount_6: std_logic;
    signal w_gcount_7: std_logic;
    signal w_gcount_8: std_logic;
    signal w_gcount_9: std_logic;
    signal r_gcount_0: std_logic;
    signal r_gcount_1: std_logic;
    signal r_gcount_2: std_logic;
    signal r_gcount_3: std_logic;
    signal r_gcount_4: std_logic;
    signal r_gcount_5: std_logic;
    signal r_gcount_6: std_logic;
    signal r_gcount_7: std_logic;
    signal r_gcount_8: std_logic;
    signal r_gcount_9: std_logic;
    signal w_gcount_r20: std_logic;
    signal w_gcount_r0: std_logic;
    signal w_gcount_r21: std_logic;
    signal w_gcount_r1: std_logic;
    signal w_gcount_r22: std_logic;
    signal w_gcount_r2: std_logic;
    signal w_gcount_r23: std_logic;
    signal w_gcount_r3: std_logic;
    signal w_gcount_r24: std_logic;
    signal w_gcount_r4: std_logic;
    signal w_gcount_r25: std_logic;
    signal w_gcount_r5: std_logic;
    signal w_gcount_r26: std_logic;
    signal w_gcount_r6: std_logic;
    signal w_gcount_r27: std_logic;
    signal w_gcount_r7: std_logic;
    signal w_gcount_r28: std_logic;
    signal w_gcount_r8: std_logic;
    signal w_gcount_r29: std_logic;
    signal w_gcount_r9: std_logic;
    signal r_gcount_w20: std_logic;
    signal r_gcount_w0: std_logic;
    signal r_gcount_w21: std_logic;
    signal r_gcount_w1: std_logic;
    signal r_gcount_w22: std_logic;
    signal r_gcount_w2: std_logic;
    signal r_gcount_w23: std_logic;
    signal r_gcount_w3: std_logic;
    signal r_gcount_w24: std_logic;
    signal r_gcount_w4: std_logic;
    signal r_gcount_w25: std_logic;
    signal r_gcount_w5: std_logic;
    signal r_gcount_w26: std_logic;
    signal r_gcount_w6: std_logic;
    signal r_gcount_w27: std_logic;
    signal r_gcount_w7: std_logic;
    signal r_gcount_w28: std_logic;
    signal r_gcount_w8: std_logic;
    signal r_gcount_w29: std_logic;
    signal r_gcount_w9: std_logic;
    signal empty_i: std_logic;
    signal rRst: std_logic;
    signal full_i: std_logic;
    signal iwcount_0: std_logic;
    signal iwcount_1: std_logic;
    signal w_gctr_ci: std_logic;
    signal iwcount_2: std_logic;
    signal iwcount_3: std_logic;
    signal co0: std_logic;
    signal iwcount_4: std_logic;
    signal iwcount_5: std_logic;
    signal co1: std_logic;
    signal iwcount_6: std_logic;
    signal iwcount_7: std_logic;
    signal co2: std_logic;
    signal iwcount_8: std_logic;
    signal iwcount_9: std_logic;
    signal co4: std_logic;
    signal wcount_9: std_logic;
    signal co3: std_logic;
    signal scuba_vhi: std_logic;
    signal ircount_0: std_logic;
    signal ircount_1: std_logic;
    signal r_gctr_ci: std_logic;
    signal ircount_2: std_logic;
    signal ircount_3: std_logic;
    signal co0_1: std_logic;
    signal ircount_4: std_logic;
    signal ircount_5: std_logic;
    signal co1_1: std_logic;
    signal ircount_6: std_logic;
    signal ircount_7: std_logic;
    signal co2_1: std_logic;
    signal ircount_8: std_logic;
    signal ircount_9: std_logic;
    signal co4_1: std_logic;
    signal rcount_9: std_logic;
    signal co3_1: std_logic;
    signal rden_i: std_logic;
    signal cmp_ci: std_logic;
    signal wcount_r0: std_logic;
    signal wcount_r1: std_logic;
    signal rcount_0: std_logic;
    signal rcount_1: std_logic;
    signal co0_2: std_logic;
    signal wcount_r2: std_logic;
    signal wcount_r3: std_logic;
    signal rcount_2: std_logic;
    signal rcount_3: std_logic;
    signal co1_2: std_logic;
    signal wcount_r4: std_logic;
    signal wcount_r5: std_logic;
    signal rcount_4: std_logic;
    signal rcount_5: std_logic;
    signal co2_2: std_logic;
    signal w_g2b_xor_cluster_0: std_logic;
    signal wcount_r7: std_logic;
    signal rcount_6: std_logic;
    signal rcount_7: std_logic;
    signal co3_2: std_logic;
    signal wcount_r8: std_logic;
    signal empty_cmp_clr: std_logic;
    signal rcount_8: std_logic;
    signal empty_cmp_set: std_logic;
    signal empty_d: std_logic;
    signal empty_d_c: std_logic;
    signal wren_i: std_logic;
    signal cmp_ci_1: std_logic;
    signal rcount_w0: std_logic;
    signal rcount_w1: std_logic;
    signal wcount_0: std_logic;
    signal wcount_1: std_logic;
    signal co0_3: std_logic;
    signal rcount_w2: std_logic;
    signal rcount_w3: std_logic;
    signal wcount_2: std_logic;
    signal wcount_3: std_logic;
    signal co1_3: std_logic;
    signal rcount_w4: std_logic;
    signal rcount_w5: std_logic;
    signal wcount_4: std_logic;
    signal wcount_5: std_logic;
    signal co2_3: std_logic;
    signal r_g2b_xor_cluster_0: std_logic;
    signal rcount_w7: std_logic;
    signal wcount_6: std_logic;
    signal wcount_7: std_logic;
    signal co3_3: std_logic;
    signal rcount_w8: std_logic;
    signal full_cmp_clr: std_logic;
    signal wcount_8: std_logic;
    signal full_cmp_set: std_logic;
    signal full_d: std_logic;
    signal full_d_c: std_logic;
    signal scuba_vlo: std_logic;

    -- local component declarations
    component AGEB2
        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
            B1: in  std_logic; CI: in  std_logic; GE: out  std_logic);
    end component;
    component AND2
        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
    end component;
    component CU2
        port (CI: in  std_logic; PC0: in  std_logic; PC1: in  std_logic; 
            CO: out  std_logic; NC0: out  std_logic; NC1: out  std_logic);
    end component;
    component FADD2B
        port (A0: in  std_logic; A1: in  std_logic; B0: in  std_logic; 
            B1: in  std_logic; CI: in  std_logic; COUT: out  std_logic; 
            S0: out  std_logic; S1: out  std_logic);
    end component;
    component FD1P3BX
    -- synopsys translate_off
        generic (GSR : in String);
    -- synopsys translate_on
        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
            PD: in  std_logic; Q: out  std_logic);
    end component;
    component FD1P3DX
    -- synopsys translate_off
        generic (GSR : in String);
    -- synopsys translate_on
        port (D: in  std_logic; SP: in  std_logic; CK: in  std_logic; 
            CD: in  std_logic; Q: out  std_logic);
    end component;
    component FD1S3BX
    -- synopsys translate_off
        generic (GSR : in String);
    -- synopsys translate_on
        port (D: in  std_logic; CK: in  std_logic; PD: in  std_logic; 
            Q: out  std_logic);
    end component;
    component FD1S3DX
    -- synopsys translate_off
        generic (GSR : in String);
    -- synopsys translate_on
        port (D: in  std_logic; CK: in  std_logic; CD: in  std_logic; 
            Q: out  std_logic);
    end component;
    component INV
        port (A: in  std_logic; Z: out  std_logic);
    end component;
    component OR2
        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
    end component;
    component ROM16X1
    -- synopsys translate_off
        generic (initval : in String);
    -- synopsys translate_on
        port (AD3: in  std_logic; AD2: in  std_logic; AD1: in  std_logic; 
            AD0: in  std_logic; DO0: out  std_logic);
    end component;
    component VHI
        port (Z: out  std_logic);
    end component;
    component VLO
        port (Z: out  std_logic);
    end component;
    component XOR2
        port (A: in  std_logic; B: in  std_logic; Z: out  std_logic);
    end component;
    component PDPW16KB
    -- synopsys translate_off
        generic (CSDECODE_R : in std_logic_vector(2 downto 0); 
                CSDECODE_W : in std_logic_vector(2 downto 0); 
                GSR : in String; RESETMODE : in String; 
                REGMODE : in String; DATA_WIDTH_R : in Integer; 
                DATA_WIDTH_W : in Integer);
    -- synopsys translate_on
        port (DI0: in  std_logic; DI1: in  std_logic; DI2: in  std_logic; 
            DI3: in  std_logic; DI4: in  std_logic; DI5: in  std_logic; 
            DI6: in  std_logic; DI7: in  std_logic; DI8: in  std_logic; 
            DI9: in  std_logic; DI10: in  std_logic; DI11: in  std_logic; 
            DI12: in  std_logic; DI13: in  std_logic; 
            DI14: in  std_logic; DI15: in  std_logic; 
            DI16: in  std_logic; DI17: in  std_logic; 
            DI18: in  std_logic; DI19: in  std_logic; 
            DI20: in  std_logic; DI21: in  std_logic; 
            DI22: in  std_logic; DI23: in  std_logic; 
            DI24: in  std_logic; DI25: in  std_logic; 
            DI26: in  std_logic; DI27: in  std_logic; 
            DI28: in  std_logic; DI29: in  std_logic; 
            DI30: in  std_logic; DI31: in  std_logic; 
            DI32: in  std_logic; DI33: in  std_logic; 
            DI34: in  std_logic; DI35: in  std_logic; 
            ADW0: in  std_logic; ADW1: in  std_logic; 
            ADW2: in  std_logic; ADW3: in  std_logic; 
            ADW4: in  std_logic; ADW5: in  std_logic; 
            ADW6: in  std_logic; ADW7: in  std_logic; 
            ADW8: in  std_logic; BE0: in  std_logic; BE1: in  std_logic; 
            BE2: in  std_logic; BE3: in  std_logic; CEW: in  std_logic; 
            CLKW: in  std_logic; CSW0: in  std_logic; 
            CSW1: in  std_logic; CSW2: in  std_logic; 
            ADR0: in  std_logic; ADR1: in  std_logic; 
            ADR2: in  std_logic; ADR3: in  std_logic; 
            ADR4: in  std_logic; ADR5: in  std_logic; 
            ADR6: in  std_logic; ADR7: in  std_logic; 
            ADR8: in  std_logic; ADR9: in  std_logic; 
            ADR10: in  std_logic; ADR11: in  std_logic; 
            ADR12: in  std_logic; ADR13: in  std_logic; 
            CER: in  std_logic; CLKR: in  std_logic; CSR0: in  std_logic; 
            CSR1: in  std_logic; CSR2: in  std_logic; RST: in  std_logic; 
            DO0: out  std_logic; DO1: out  std_logic; 
            DO2: out  std_logic; DO3: out  std_logic; 
            DO4: out  std_logic; DO5: out  std_logic; 
            DO6: out  std_logic; DO7: out  std_logic; 
            DO8: out  std_logic; DO9: out  std_logic; 
            DO10: out  std_logic; DO11: out  std_logic; 
            DO12: out  std_logic; DO13: out  std_logic; 
            DO14: out  std_logic; DO15: out  std_logic; 
            DO16: out  std_logic; DO17: out  std_logic; 
            DO18: out  std_logic; DO19: out  std_logic; 
            DO20: out  std_logic; DO21: out  std_logic; 
            DO22: out  std_logic; DO23: out  std_logic; 
            DO24: out  std_logic; DO25: out  std_logic; 
            DO26: out  std_logic; DO27: out  std_logic; 
            DO28: out  std_logic; DO29: out  std_logic; 
            DO30: out  std_logic; DO31: out  std_logic; 
            DO32: out  std_logic; DO33: out  std_logic; 
            DO34: out  std_logic; DO35: out  std_logic);
    end component;
    attribute initval : string; 
    attribute MEM_LPC_FILE : string; 
    attribute MEM_INIT_FILE : string; 
    attribute CSDECODE_R : string; 
    attribute CSDECODE_W : string; 
    attribute RESETMODE : string; 
    attribute REGMODE : string; 
    attribute DATA_WIDTH_R : string; 
    attribute DATA_WIDTH_W : string; 
    attribute GSR : string; 
    attribute initval of LUT4_23 : label is "0x6996";
    attribute initval of LUT4_22 : label is "0x6996";
    attribute initval of LUT4_21 : label is "0x6996";
    attribute initval of LUT4_20 : label is "0x6996";
    attribute initval of LUT4_19 : label is "0x6996";
    attribute initval of LUT4_18 : label is "0x6996";
    attribute initval of LUT4_17 : label is "0x6996";
    attribute initval of LUT4_16 : label is "0x6996";
    attribute initval of LUT4_15 : label is "0x6996";
    attribute initval of LUT4_14 : label is "0x6996";
    attribute initval of LUT4_13 : label is "0x6996";
    attribute initval of LUT4_12 : label is "0x6996";
    attribute initval of LUT4_11 : label is "0x6996";
    attribute initval of LUT4_10 : label is "0x6996";
    attribute initval of LUT4_9 : label is "0x6996";
    attribute initval of LUT4_8 : label is "0x6996";
    attribute initval of LUT4_7 : label is "0x6996";
    attribute initval of LUT4_6 : label is "0x6996";
    attribute initval of LUT4_5 : label is "0x6996";
    attribute initval of LUT4_4 : label is "0x6996";
    attribute initval of LUT4_3 : label is "0x0410";
    attribute initval of LUT4_2 : label is "0x1004";
    attribute initval of LUT4_1 : label is "0x0140";
    attribute initval of LUT4_0 : label is "0x4001";
    attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_DC.lpc";
    attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
    attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b000";
    attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001";
    attribute GSR of pdp_ram_0_0_0 : label is "ENABLED";
    attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
    attribute REGMODE of pdp_ram_0_0_0 : label is "NOREG";
    attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36";
    attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36";
    attribute GSR of FF_101 : label is "ENABLED";
    attribute GSR of FF_100 : label is "ENABLED";
    attribute GSR of FF_99 : label is "ENABLED";
    attribute GSR of FF_98 : label is "ENABLED";
    attribute GSR of FF_97 : label is "ENABLED";
    attribute GSR of FF_96 : label is "ENABLED";
    attribute GSR of FF_95 : label is "ENABLED";
    attribute GSR of FF_94 : label is "ENABLED";