📄 getpcmdata.twr
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Lattice TRACE Report, Version ispLever_v70_Prod_Build (55)
Fri Jun 20 12:09:26 2008
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -o checkpnt.twr getpcmdata.ncd getpcmdata.prf
Design file: getpcmdata.ncd
Preference file: getpcmdata.prf
Device,speed: LCMXO640C,5
Report level: verbose report, limited to 1 item per preference
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BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "CLK_RXD" 0.468114 MHz ;
123 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
WARNING - trce: Clock skew between net 'Uart_In_c' and net 'CLK_RXD' not
computed: nets may not be related
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1042.202ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u4/rstate_5 (from CLK_RXD +)
Destination: FF Unknown u4/DataRec_8 (to CLK_RXD +)
Delay: 5.870ns (15.8% logic, 84.2% route), 3 logic levels.
Constraint Details:
5.870ns physical path delay u4/SLICE_62 to u4/SLICE_17 meets
1048.575ns delay constraint less
0.329ns skew and
0.174ns CE_SET requirement (totaling 1048.072ns) by 1042.202ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.400 R2C5A.CLK to R2C5A.Q1 u4/SLICE_62 (from CLK_RXD)
ROUTE 4 1.903 R2C5A.Q1 to R2C4D.C1 u4/rstate_5
CTOF_DEL --- 0.265 R2C4D.C1 to R2C4D.F1 SLICE_68
ROUTE 1 1.877 R2C4D.F1 to R2C6A.C1 u4/un13_rstate_0
CTOF_DEL --- 0.265 R2C6A.C1 to R2C6A.F1 SLICE_64
ROUTE 5 1.160 R2C6A.F1 to R4C8D.CE u4/un13_rstate (to CLK_RXD)
--------
5.870 (15.8% logic, 84.2% route), 3 logic levels.
Clock Skew Details:
Source Clock:
Delay Connection
1.186ns R4C7A.Q0 to R2C5A.CLK
Destination Clock :
Delay Connection
0.857ns R4C7A.Q0 to R4C8D.CLK
Report: 156.912MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "CLK_TXD" 0.117028 MHz ;
79 items scored, 0 timing errors detected.
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WARNING - trce: Clock skew between net 'WrClock' and net 'CLK_TXD' not
computed: nets may not be related
WARNING - trce: Clock skew between net 'PCM_CLK_c' and net 'CLK_TXD' not
computed: nets may not be related
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1045.217ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u2/tstate_3 (from CLK_TXD +)
Destination: FF Unknown u2/sendbuffer_1 (to CLK_TXD +)
FF u2/sendbuffer_0
Delay: 2.526ns (26.3% logic, 73.7% route), 2 logic levels.
Constraint Details:
2.526ns physical path delay u2/SLICE_53 to u2/SLICE_47 meets
1048.575ns delay constraint less
0.658ns skew and
0.174ns CE_SET requirement (totaling 1047.743ns) by 1045.217ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.400 R5C5A.CLK to R5C5A.Q1 u2/SLICE_53 (from CLK_TXD)
ROUTE 4 0.740 R5C5A.Q1 to R5C5B.B1 u2/tstate_3
CTOF_DEL --- 0.265 R5C5B.B1 to R5C5B.F1 SLICE_45
ROUTE 7 1.121 R5C5B.F1 to R4C4A.CE u2/N_34_i (to CLK_TXD)
--------
2.526 (26.3% logic, 73.7% route), 2 logic levels.
Clock Skew Details:
Source Clock:
Delay Connection
1.502ns R5C4C.Q0 to R5C5A.CLK
Destination Clock :
Delay Connection
0.844ns R5C4C.Q0 to R4C4A.CLK
Report: 297.796MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "PCM_CLK" 8.192000 MHz ;
784 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
WARNING - trce: Clock skew between net 'GetDataPC' and net 'PCM_CLK_c' not
computed: nets may not be related
WARNING - trce: Clock skew between net 'CLK_TXD' and net 'WrClock' not
computed: nets may not be related
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 107.013ns
and meets 30.517ns delay constraint requirement for source clock "GetDataPC" by 15.460ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Slot_6 (from GetDataPC +)
Destination: FF Unknown U5/L_Data (to PCM_CLK_c -)
Delay: 14.868ns (21.3% logic, 78.7% route), 5 logic levels.
Constraint Details:
14.868ns physical path delay SLICE_67 to U5/SLICE_44 meets
122.070ns delay constraint less
0.189ns CE_SET requirement (totaling 121.881ns) by 107.013ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.400 R2C4A.CLK to R2C4A.Q0 SLICE_67 (from GetDataPC)
ROUTE 2 4.834 R2C4A.Q0 to R2C8D.A0 Slot_6
TLATCH_DEL --- 1.445 R2C8D.A0 to R2C8D.Q1 U5/SLICE_7
ROUTE 1 3.162 R2C8D.Q1 to R2C9B.A1 U5/un16_chunnel_a_4_7
A1TOCOUT_D --- 0.787 R2C9B.A1 to R2C9B.OFX1 SLICE_1
ROUTE 2 0.963 R2C9B.OFX1 to R4C8B.C1 U5/data_tmp_3
CTOF_DEL --- 0.265 R4C8B.C1 to R4C8B.F1 U5/SLICE_44
ROUTE 5 0.793 R4C8B.F1 to R4C9A.B0 U5/un12_chunnel
CTOF_DEL --- 0.265 R4C9A.B0 to R4C9A.F0 SLICE_66
ROUTE 1 1.954 R4C9A.F0 to R4C8B.CE U5/L_Data_1_sqmuxa_i (to PCM_CLK_c)
--------
14.868 (21.3% logic, 78.7% route), 5 logic levels.
Clock Skew Details:
Source Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.759 55.PAD to 55.PADDI Clock
ROUTE 5 1.018 55.PADDI to R4C7A.CLK Clock_c
REG_DEL --- 0.400 R4C7A.CLK to R4C7A.Q0 U3/SLICE_10
ROUTE 17 1.515 R4C7A.Q0 to R2C4B.CLK CLK_RXD
REG_DEL --- 0.400 R2C4B.CLK to R2C4B.Q0 u4/SLICE_18
ROUTE 6 0.514 R2C4B.Q0 to R2C4A.CLK GetDataPC
--------
4.606 (33.8% logic, 66.2% route), 3 logic levels.
Destination Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.759 144.PAD to 144.PADDI PCM_CLK
ROUTE 15 2.480 144.PADDI to R4C8B.CLK PCM_CLK_c
--------
3.239 (23.4% logic, 76.6% route), 1 logic levels.
Report: 66.414MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "Clock" 32.768000 MHz HOLD_MARGIN 3.000000 nS ;
191 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
WARNING - trce: Clock skew between net 'PCM_CLK_c' and net 'GetDataPC' not
computed: nets may not be related
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 20.624ns
and meets 122.070ns delay constraint requirement for source clock "PCM_CLK_c" by 112.177ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q U5/count_2 (from PCM_CLK_c -)
Destination: FF Unknown U5/un16_chunnel_0_I_19_0 (to GetDataPC +)
Delay: 9.414ns (27.8% logic, 72.2% route), 5 logic levels.
Constraint Details:
9.414ns physical path delay U5/SLICE_37 to SLICE_1 meets
30.517ns delay constraint less
0.479ns FCI_SET requirement (totaling 30.038ns) by 20.624ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.438 R3C8D.CLK to R3C8D.Q0 U5/SLICE_37 (from PCM_CLK_c)
ROUTE 2 0.907 R3C8D.Q0 to R3C8B.D1 U5/count_2
CTOF_DEL --- 0.265 R3C8B.D1 to R3C8B.F1 SLICE_59
ROUTE 1 0.766 R3C8B.F1 to R3C9A.M0 U5/un2_count
TLATCH_DEL --- 1.017 R3C9A.M0 to R3C9A.Q0 U5/SLICE_6
ROUTE 2 1.470 R3C9A.Q0 to R3C8B.B0 U5/un1_chunnel_cry_0_0_S0
CTOF_DEL --- 0.265 R3C8B.B0 to R3C8B.F0 SLICE_59
ROUTE 1 3.656 R3C8B.F0 to R2C9A.C0 U5/N_32
C0TOFCO_DE --- 0.630 R2C9A.C0 to R2C9A.FCO SLICE_2
ROUTE 1 0.000 R2C9A.FCO to R2C9B.FCI U5/data_tmp_1 (to GetDataPC)
--------
9.414 (27.8% logic, 72.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.759 144.PAD to 144.PADDI PCM_CLK
ROUTE 15 2.480 144.PADDI to R3C8D.CLK PCM_CLK_c
--------
3.239 (23.4% logic, 76.6% route), 1 logic levels.
Destination Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.759 55.PAD to 55.PADDI Clock
ROUTE 5 1.018 55.PADDI to R4C7A.CLK Clock_c
REG_DEL --- 0.400 R4C7A.CLK to R4C7A.Q0 U3/SLICE_10
ROUTE 17 1.515 R4C7A.Q0 to R2C4B.CLK CLK_RXD
REG_DEL --- 0.400 R2C4B.CLK to R2C4B.Q0 u4/SLICE_18
ROUTE 6 1.874 R2C4B.Q0 to R2C9B.CLK GetDataPC
--------
5.966 (26.1% logic, 73.9% route), 3 logic levels.
Report: 101.082MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "CLK_RXD" 0.468114 MHz ; | 0.468 MHz| 156.912 MHz| 3
| | |
FREQUENCY NET "CLK_TXD" 0.117028 MHz ; | 0.117 MHz| 297.796 MHz| 2
| | |
FREQUENCY PORT "PCM_CLK" 8.192000 MHz ; | 8.192 MHz| 66.414 MHz| 5
| | |
FREQUENCY PORT "Clock" 32.768000 MHz | | |
HOLD_MARGIN 3.000000 nS ; | 32.768 MHz| 101.082 MHz| 5
| | |
----------------------------------------------------------------------------
All preferences were met.
Timing summary:
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1177 paths, 8 nets, and 422 connections (91.5% coverage)
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