📄 getpcmdata_bgn.html
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<HEAD><TITLE>Bitgen Report</TITLE>
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<A name="Bgn"></A>BITGEN: Bitstream Generator ispLever_v70_SP2_Build (24)
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation, All rights reserved.
Command: bitgen -g DisableUES:FALSE -g RamCfg:Reset -w -jedec -e -s getpcmdata.sec -k getpcmdata.bek getpcmdata.ncd getpcmdata.prf
Loading design for application Bitgen from file getpcmdata.ncd.
Design name: GetPcm
NCD version: 3.2
Vendor: LATTICE
Device: LFXP2-17E
Package: PQFP208
Speed: 5
Loading device for application Bitgen from file 'mg5a50x47.nph' in
environment: D:/ispTOOLS7_0/ispfpga.
Package: Version 1.60, Status: FINAL
Speed Hardware Data: version 1.67.1.5
Running DRC.
WARNING - blockcheck: Pin FCI on component u1/SLICE_5 has no signal but is
used inside the comp.
WARNING - blockcheck: Pin FCI on component u1/SLICE_21 has no signal but is
used inside the comp.
WARNING - blockcheck: Pin FCI on component u1/SLICE_27 has no signal but is
used inside the comp.
WARNING - blockcheck: Pin FCI on component u1/SLICE_28 has no signal but is
used inside the comp.
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The
use of the EBR block asynchronous reset requires that certain timing be met
between the clock and the reset within the memory block. See the device
specific datasheet for additional details.
DRC detected 0 errors and 4 warnings.
Reading Preference File from getpcmdata.prf...
<A name="bgn_ps"></A>
<B><U><big>Preference Summary:</big></U></B>
+---------------------------------+---------------------------------+
| Preference | Current Setting |
+---------------------------------+---------------------------------+
| RamCfg | Reset** |
+---------------------------------+---------------------------------+
| DONE_EX | OFF** |
+---------------------------------+---------------------------------+
| DONE_OD | ON** |
+---------------------------------+---------------------------------+
| MCCLK_FREQ | 3.1** |
+---------------------------------+---------------------------------+
| CONFIG_SECURE | OFF** |
+---------------------------------+---------------------------------+
| WAKE_UP | 21** |
+---------------------------------+---------------------------------+
| WAKE_ON_LOCK | OFF** |
+---------------------------------+---------------------------------+
| INBUF | ON** |
+---------------------------------+---------------------------------+
| ENABLE_NDR | OFF** |
+---------------------------------+---------------------------------+
| MY_ASSP | OFF** |
+---------------------------------+---------------------------------+
| ONE_TIME_PROGRAM | OFF** |
+---------------------------------+---------------------------------+
| SLAVE_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| MASTER_SPI_PORT | DISABLE** |
+---------------------------------+---------------------------------+
| DisableUES | FALSE** |
+---------------------------------+---------------------------------+
* Default setting.
** The specified setting matches the default setting.
Creating bit map...
Saving bit stream in "getpcmdata.jed".
Generated from the file 'D:\CPLD\FPGA\GetPcm\getpcmdata.bgn'
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