fifo_dc_tmpl.vhd

来自「PCM数据采集」· VHDL 代码 · 共 19 行

-- VHDL module instantiation generated by SCUBA ispLever_v70_SP2_Build (24)
-- Module  Version: 4.3
-- Wed Jun 18 17:17:15 2008

-- parameterized module component declaration
component FIFO_DC
    port (Data: in  std_logic_vector(8 downto 0); WrClock: in  std_logic; 
        RdClock: in  std_logic; WrEn: in  std_logic; RdEn: in  std_logic; 
        Reset: in  std_logic; RPReset: in  std_logic; 
        Q: out  std_logic_vector(8 downto 0); Empty: out  std_logic; 
        Full: out  std_logic);
end component;

-- parameterized module component instance
__ : FIFO_DC
    port map (Data(8 downto 0)=>__, WrClock=>__, RdClock=>__, WrEn=>__, 
        RdEn=>__, Reset=>__, RPReset=>__, Q(8 downto 0)=>__, Empty=>__, 
        Full=>__);