5_1.par

PCM数据采集

Lattice Place and Route Report for Design "getpcmdata_map.ncd"
Fri Jun 20 12:08:52 2008

PAR: Place And Route ispLever_v70_Prod_Build (55).
Command line: D:/ispTOOLS7_0/ispfpga\bin\nt\par -f getpcmdata.p2t getpcmdata_map.ncd
getpcmdata.dir getpcmdata.prf
Preference file: getpcmdata.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file getpcmdata_map.ncd.
Design name: GetPcm
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO640C
Package:     TQFP144
Speed:       5
Loading device for application par from file 'mj5g12x10.nph' in environment
D:/ispTOOLS7_0/ispfpga.
Package: Version 1.15, Status: FINAL
Speed Hardware Data: version 1.80


Ignore Preference Error(s):  True
Dumping design to file F:/Temp/Tmp/neo_2.
Device utilization summary:


   PIO               17/160          10% used
                     17/113          15% bonded

   SLICE             60/320          18% used

   GSR                1/1           100% used


Number of Signals: 199
Number of Connections: 461

Pin Constraint Summary:
   17 out of 17 pins locked (100% locked).

The following 1 signal is selected to use the primary clock routing resource:
    Clock_c (driver: Clock, clk load #: 5)

The following 1 signal is selected to use the secondary clock routing resource:
    PCM_CLK_c (driver: PCM_CLK, clk load #: 15, sr load #: 0, ce load #: 0)

WARNING - par: Signal "PCM_CLK_c" is selected to use Secondary clock
          resources; however its driver comp "PCM_CLK" is located at "144",
          which is not a dedicated pin for connecting to Secondary clock
          resources.  General routing has to be used to route this signal,
          and it may suffer from excessive delay or skew.
Signal Reset_c is selected as Global Set/Reset.
Starting Placer Phase 0.

Finished Placer Phase 0.  REAL time: 8 secs 

Starting Placer Phase 1.
Placer score = 2229667.
...........................
Placer score = 416152.
Finished Placer Phase 1.  REAL time: 21 secs 

Starting Placer Phase 2.
.
Placer score =  415934
Finished Placer Phase 2.  REAL time: 22 secs 


------------------ Clock Report ------------------

Global Clock Resources:
  CLK_PIN    : 1 out of 4 (25%)
  General PIO: 1 out of 160 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "Clock_c" from CLK_PIN "55", driver "Clock", clk load = 5
  SECONDARY "PCM_CLK_c" from PIO "144", driver "PCM_CLK", clk load = 15, ce load = 0, sr load = 0

  PRIMARY  : 1 out of 4 (25%)
  SECONDARY: 1 out of 4 (25%)

--------------- End of Clock Report ---------------


I/O Usage Summary:
   17 out of 160 (10%) PIO sites used.
   17 out of 113 (15%) bonded PIO sites used.
   Number of PIO comps: 17; differential: 0
   Number of Vref pins used: 0

Total placer CPU time: 14 secs 

Dumping design to file getpcmdata.dir/5_1.ncd.

0 connections routed; 461 unrouted.
Starting router resource preassignment
Clock Skew Minimization: OFF
WARNING - par: The driver of secondary clock net PCM_CLK_c is not placed on
          one of the PIO sites which are dedicated for secondary clocks. 
          This secondary clock will be routed through general routing
          resource and may suffer from excessive delay or skew.
Completed router resource preassignment. Real time: 22 secs 
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
461 successful; 0 unrouted; (0) real time: 22 secs 
Dumping design to file getpcmdata.dir/5_1.ncd.

Hold time optimization iteration 0:
There are 97 hold time violations, the optimization is running ...
End of iteration 0
461 successful; 0 unrouted; (0) real time: 33 secs 
Dumping design to file getpcmdata.dir/5_1.ncd.

Hold time optimization iteration 1:
All hold time violations have been successfully corrected in speed grade M

---------------IO Configurable Delay Element Usage Summary---------------

Total IO Configurable Delay Elements used: 0 
---------------End of IO Configurable Delay Element Usage Summary--------

Dumping design to file getpcmdata.dir/5_1.ncd.
Total CPU time 25 secs 
Total REAL time: 33 secs 
Completely routed.
End of route.  461 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.
Timing score: 0 

Total REAL time to completion: 33 secs 


All signals are completely routed.


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