baudr.vhm

PCM数据采集

--
-- Written by Synplicity
-- Product Version "Version 9.0L1"
-- Program "Synplify", Mapper "9.0.0, Build 139R"
-- Wed Jun 18 10:49:09 2008
--

--
-- Written by Synplify version 9.0.0, Build 139R
-- Wed Jun 18 10:49:09 2008
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library xp2;
use xp2.components.all;

entity BaudR is
port(
  Reset :  in std_logic;
  Clock :  in std_logic;
  CLK_RXD :  out std_logic;
  CLK_TXD :  out std_logic);
end BaudR;

architecture beh of BaudR is
  signal \GET_CLK_RXD.COUNT\ : std_logic_vector(5 downto 0);
  signal \GET_CLK_TXD.COUNT\ : std_logic_vector(0 to 0);
  signal COUNT_3 : std_logic_vector(5 downto 0);
  signal COUNT_QN : std_logic_vector(5 downto 0);
  signal COUNT_QN_0 : std_logic_vector(1 downto 0);
  signal \GET_CLK_TXD.COUNT_I\ : std_logic_vector(0 to 0);
  signal \GET_CLK_RXD.UN4_COUNT\ : std_logic ;
  signal CLK_RXD_I : std_logic ;
  signal SUM1 : std_logic ;
  signal UN8_COUNT_AXBXC2 : std_logic ;
  signal UN8_COUNT_AXBXC3 : std_logic ;
  signal UN8_COUNT_AXBXC4 : std_logic ;
  signal UN8_COUNT_P4 : std_logic ;
  signal \GET_CLK_RXD.UN4_COUNT_1_0\ : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal RESET_C : std_logic ;
  signal CLOCK_C : std_logic ;
  signal CLK_RXD_C : std_logic ;
  signal CLK_TXD_C : std_logic ;
  signal CLK_RXD_QN : std_logic ;
  signal CLK_RXD_C_I : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  PUR_INST: PUR port map (
      PUR => VCC);
  VCC_0: VHI port map (
      Z => VCC);
  GND_0: VLO port map (
      Z => GND);
  \GET_CLK_TXD.COUNT_I[0]_Z50\: INV port map (
      A => \GET_CLK_TXD.COUNT\(0),
      Z => \GET_CLK_TXD.COUNT_I\(0));
  CLK_RXD_C_I_Z51: INV port map (
      A => CLK_RXD_C,
      Z => CLK_RXD_C_I);
  \GET_CLK_TXD.COUNT[0]_REG\: FD1S3AX port map (
      D => \GET_CLK_TXD.COUNT_I\(0),
      CK => CLK_RXD_C,
      Q => \GET_CLK_TXD.COUNT\(0));
  \GET_CLK_TXD.COUNT[1]_REG\: FD1S3AX port map (
      D => SUM1,
      CK => CLK_RXD_C,
      Q => CLK_TXD_C);
  \GET_CLK_RXD.COUNT[0]_REG\: FD1S3AX port map (
      D => COUNT_3(0),
      CK => CLOCK_C,
      Q => \GET_CLK_RXD.COUNT\(0));
  \GET_CLK_RXD.COUNT[1]_REG\: FD1S3AX port map (
      D => COUNT_3(1),
      CK => CLOCK_C,
      Q => \GET_CLK_RXD.COUNT\(1));
  \GET_CLK_RXD.COUNT[2]_REG\: FD1S3AX port map (
      D => UN8_COUNT_AXBXC2,
      CK => CLOCK_C,
      Q => \GET_CLK_RXD.COUNT\(2));
  \GET_CLK_RXD.COUNT[3]_REG\: FD1S3AX port map (
      D => UN8_COUNT_AXBXC3,
      CK => CLOCK_C,
      Q => \GET_CLK_RXD.COUNT\(3));
  \GET_CLK_RXD.COUNT[4]_REG\: FD1S3AX port map (
      D => UN8_COUNT_AXBXC4,
      CK => CLOCK_C,
      Q => \GET_CLK_RXD.COUNT\(4));
  \GET_CLK_RXD.COUNT[5]_REG\: FD1S3AX port map (
      D => COUNT_3(5),
      CK => CLOCK_C,
      Q => \GET_CLK_RXD.COUNT\(5));
  CLK_RXD_REG: FD1P3AX port map (
      D => CLK_RXD_C_I,
      SP => \GET_CLK_RXD.UN4_COUNT\,
      CK => CLOCK_C,
      Q => CLK_RXD_I);
  GSR_INST: GSR port map (
      GSR => RESET_C);
  CLK_TXD_PAD: OB port map (
      I => CLK_TXD_C,
      O => CLK_TXD);
  CLK_RXD_PAD: OB port map (
      I => CLK_RXD_C,
      O => CLK_RXD);
  CLOCK_PAD: IB port map (
      I => Clock,
      O => CLOCK_C);
  RESET_PAD: IB port map (
      I => Reset,
      O => RESET_C);
  UN8_COUNT_P4 <= \GET_CLK_RXD.COUNT\(0) and \GET_CLK_RXD.COUNT\(1) and \GET_CLK_RXD.COUNT\(2) and \GET_CLK_RXD.COUNT\(3);
  SUM1 <= (\GET_CLK_TXD.COUNT\(0) and not CLK_TXD_C) or 
	  (not \GET_CLK_TXD.COUNT\(0) and CLK_TXD_C);
  UN8_COUNT_AXBXC4 <= (\GET_CLK_RXD.COUNT\(4) and not UN8_COUNT_P4) or 
	  (not \GET_CLK_RXD.COUNT\(4) and UN8_COUNT_P4);
  UN8_COUNT_AXBXC2 <= (\GET_CLK_RXD.COUNT\(0) and \GET_CLK_RXD.COUNT\(1) and not \GET_CLK_RXD.COUNT\(2)) or 
	  (not \GET_CLK_RXD.COUNT\(1) and \GET_CLK_RXD.COUNT\(2)) or 
	  (not \GET_CLK_RXD.COUNT\(0) and \GET_CLK_RXD.COUNT\(2));
  UN8_COUNT_AXBXC3 <= (\GET_CLK_RXD.COUNT\(0) and \GET_CLK_RXD.COUNT\(1) and \GET_CLK_RXD.COUNT\(2) and not \GET_CLK_RXD.COUNT\(3)) or 
	  (not \GET_CLK_RXD.COUNT\(2) and \GET_CLK_RXD.COUNT\(3)) or 
	  (not \GET_CLK_RXD.COUNT\(1) and \GET_CLK_RXD.COUNT\(3)) or 
	  (not \GET_CLK_RXD.COUNT\(0) and \GET_CLK_RXD.COUNT\(3));
  COUNT_3(0) <= not \GET_CLK_RXD.COUNT\(0) and not \GET_CLK_RXD.UN4_COUNT\;
  COUNT_3(1) <= (\GET_CLK_RXD.COUNT\(0) and not \GET_CLK_RXD.COUNT\(1) and not \GET_CLK_RXD.UN4_COUNT\) or 
	  (not \GET_CLK_RXD.COUNT\(0) and \GET_CLK_RXD.COUNT\(1) and not \GET_CLK_RXD.UN4_COUNT\);
  \GET_CLK_RXD.UN4_COUNT_1_0\ <= not \GET_CLK_RXD.COUNT\(4) and \GET_CLK_RXD.COUNT\(5);
  \GET_CLK_RXD.UN4_COUNT\ <= \GET_CLK_RXD.COUNT\(1) and not \GET_CLK_RXD.COUNT\(2) and not \GET_CLK_RXD.COUNT\(3) and \GET_CLK_RXD.UN4_COUNT_1_0\;
  COUNT_3(5) <= (\GET_CLK_RXD.COUNT\(5) and not \GET_CLK_RXD.UN4_COUNT\ and not UN8_COUNT_P4) or 
	  (\GET_CLK_RXD.COUNT\(4) and not \GET_CLK_RXD.COUNT\(5) and not \GET_CLK_RXD.UN4_COUNT\ and UN8_COUNT_P4) or 
	  (not \GET_CLK_RXD.COUNT\(4) and \GET_CLK_RXD.COUNT\(5) and not \GET_CLK_RXD.UN4_COUNT\);
  CLK_RXD_C <= CLK_RXD_I;
  NN_1 <= '0';
  NN_2 <= '1';
end beh;