uart.vhd.bak

PCM数据采集

library ieee;
use ieee.std_logic_1164.all;

entity UART is
Port(
	RES,WRXD,clk				:in std_logic;
	TXD,ErroLED,SendLED	        :out std_logic;
	m113777,m455108				:buffer std_logic;
	ReData                      :buffer std_logic_vector(8 downto 0)
	);
end entity;

architecture ART_UART of UART is
--signal Data 	:std_logic_vector(8 downto 0);
signal DataOK	:std_logic;
component PRXD
Port(
    RESET       :in  std_logic;
    RCLK,RXD	:in  std_logic;
    ReBuf    	:out std_logic_vector(8 downto 0);
	GetData		:buffer std_logic;
	Err			:out std_logic
	);
end component;

component PTXD
Port(
    TCLK	    :in  std_logic;
    wen         :in  std_logic;
    tbr         :in  std_logic_vector(8 downto 0);
	dout        :out std_logic;
	tre         :buffer std_logic    
	);
end component;

component Baudr
Port(
	Clock	:in  std_logic;
	baud4	:buffer std_logic;
	baud	:buffer std_logic
	);
end component;

begin
	PTXD_1:
	PTXD port map
		(
		TCLK=>m113777,
    	wen=>DataOK,
    --	RESET=>RES, 
    	tbr=>ReData,
		dout=>TXD,
		tre=>SendLED
		);
	PRXD_1:
	PRXD port map
		(
		RESET=>RES,
		RCLK=>m455108,
		RXD=>WRXD,
    	ReBuf=>ReData,
		GetData=>DataOK,
		Err=>ErroLED
		);
	Baudr_1:
	Baudr port map
		(
		Clock=>clk,
		baud4=>m455108,
		baud=>m113777
		);	

end ART_UART;