pcm.log

PCM数据采集

#Build: Synplify for Lattice 8.8L2, Build 008R, Dec  7 2006
#install: D:\ISPTOOLS7_0\SYNPBASE
#OS: Windows XP 5.1
#Hostname: STAR-PANCAT

#Implementation: getpcm

#Thu Jun 19 11:12:48 2008

$ Start of Compile
#Thu Jun 19 11:12:48 2008

Synplicity VHDL Compiler, version 3.7.5, Build 159R, built Apr 13 2007
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved

@N: CD720 :"D:\ISPTOOLS7_0\SYNPBASE\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"D:\cpld\fpga\getpcm\pcm.vhd":6:7:6:9|Top entity is set to PCM.
VHDL syntax check successful!
@N: CD630 :"D:\cpld\fpga\getpcm\pcm.vhd":6:7:6:9|Synthesizing work.pcm.art_pcm 
Post processing for work.pcm.art_pcm
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jun 19 11:12:48 2008

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Synplicity Generic Technology Mapper, Version 8.8.0, Build 018R, Built Apr 17 2007 19:29:01
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved
Product Version Version 8.8L2
@N: MF249 |Running in 32-bit mode.


RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)
@N:"d:\cpld\fpga\getpcm\pcm.vhd":61:2:61:3|Found counter in view:work.PCM(art_pcm) inst chunnel[7:0]
@N:"d:\cpld\fpga\getpcm\pcm.vhd":61:2:61:3|Found counter in view:work.PCM(art_pcm) inst count[2:0]
@N: MF179 :|Found 8 bit by 8 bit '==' comparator, 'un7_chunnel'

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Clock Buffers:
  Inserting Clock buffer for port PCLK,	TNM=PCLK


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 51MB)

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		    -2.04ns		  26 /        29
   2		0h:00m:00s		    -2.04ns		  26 /        29
   3		0h:00m:00s		    -2.04ns		  26 /        29
------------------------------------------------------------

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		    -1.50ns		  29 /        29
Timing driven replication report
No replication required.

   2		0h:00m:00s		    -1.50ns		  29 /        29
   3		0h:00m:00s		    -1.50ns		  29 /        29
   4		0h:00m:00s		    -1.50ns		  29 /        29
------------------------------------------------------------

Timing driven replication report
No replication required.

Timing driven replication report
No replication required.

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		    -1.50ns		  29 /        29
Timing driven replication report
No replication required.

   2		0h:00m:00s		    -1.50ns		  29 /        29
   3		0h:00m:00s		    -1.50ns		  29 /        29
   4		0h:00m:00s		    -1.50ns		  29 /        29
------------------------------------------------------------

Net buffering Report for view:work.PCM(art_pcm):
No nets needed buffering.


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)
Found clock PCM|PCLK with period 5.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Jun 19 11:12:50 2008
#


Top view:               PCM
Requested Frequency:    200.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..


Performance Summary 
*******************


Worst slack in design: -1.498

                   Requested     Estimated     Requested     Estimated                Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group              
----------------------------------------------------------------------------------------------------------------------
PCM|PCLK           200.0 MHz     153.9 MHz     5.000         6.498         -1.498     inferred     Inferred_clkgroup_0
System             200.0 MHz     467.6 MHz     5.000         2.139         2.861      system       default_clkgroup   
======================================================================================================================





Clock Relationships
*******************

Clocks              |    rise  to  rise   |    fall  to  fall    |    rise  to  fall   |    fall  to  rise 
-----------------------------------------------------------------------------------------------------------
Starting  Ending    |  constraint  slack  |  constraint  slack   |  constraint  slack  |  constraint  slack
-----------------------------------------------------------------------------------------------------------
PCM|PCLK  PCM|PCLK  |  No paths    -      |  5.000       -1.498  |  No paths    -      |  No paths    -    
===========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port        Starting            User           Arrival     Required          
Name        Reference           Constraint     Time        Time         Slack
            Clock                                                            
-----------------------------------------------------------------------------
FSYNC       System (rising)     NA             0.000       0.357             
PCLK        NA                  NA             NA          NA           NA   
Reset       System (rising)     NA             0.000       2.861             
S_Data      System (rising)     NA             0.000       3.153             
Slot[0]     System (rising)     NA             0.000       -1.498            
Slot[1]     System (rising)     NA             0.000       -1.498            
Slot[2]     System (rising)     NA             0.000       -1.460            
Slot[3]     System (rising)     NA             0.000       -1.460            
Slot[4]     System (rising)     NA             0.000       -0.530            
Slot[5]     System (rising)     NA             0.000       -1.413            
Slot[6]     System (rising)     NA             0.000       -1.217            
Slot[7]     System (rising)     NA             0.000       -0.249            
=============================================================================


Output Ports: 

Port            Starting               User           Arrival     Required          
Name            Reference              Constraint     Time        Time         Slack
                Clock                                                               
------------------------------------------------------------------------------------
L_Data          PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[0]     PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[1]     PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[2]     PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[3]     PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[4]     PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[5]     PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[6]     PCM|PCLK (falling)     NA             4.187       5.000             
PCM_Data[7]     PCM|PCLK (falling)     NA             4.187       5.000             
====================================================================================


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report
Part: lfxp2_17e-5

Register bits: 29 of 16560 (0%)
I/O cells:       21

Details:
CCU2B:          8
FD1P3AX:        15
FD1S3AX:        4
GSR:            1
IB:             12
IFS1P3DX:       1
INV:            1
OB:             9
OFS1P3DX:       9
ORCALUT4:       27
VHI:            1
VLO:            1

Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)
Writing Analyst data base D:\cpld\fpga\getpcm\PCM.srm
@N: MF203 |Set autoconstraint_io 
Writing EDIF Netlist and constraint files
@N: MF203 |Set autoconstraint_io 
Version 8.8L2
Writing Verilog Simulation files
@N: MF203 |Set autoconstraint_io 
Writing VHDL Simulation files
@N: MF203 |Set autoconstraint_io 
@N: MF203 |Set autoconstraint_io 
Mapper successful!
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Thu Jun 19 11:12:51 2008

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