getpcm.vhd.bak

PCM数据采集

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity GetPcm is

port( 
	Reset: in std_logic ;
	Clock: in std_logic ;
	Uart_In :in std_logic;
	Uart_Out :out std_logic;
	PCM_CLK: in std_logic ;
	PCM_Fsync: in std_logic ;
	PCM_Din: in std_logic ;
	PCM_Dout: in std_logic  );

end;

architecture ART_GetPcm of GetPcm is
-----------------------------------------------------------------
    component UartSend
		port( 
			Reset	: in std_logic ;
			SendClk	: in std_logic ;
			Data	: in std_logic_vector( 8 downto 0 );
			Latch	: in std_logic ;
			UartOut	: out std_logic ;
			Busy	: out std_logic  
			);
    end component;
-----------------------------------------------------------------    			
	component BaudR
		Port(
			Reset	:in	std_logic;	--low 
			Clock	:in  std_logic;  	--32.768Mhz
			CLK_RXD	:buffer std_logic;	--468114Hz
			CLK_TXD	:out std_logic	--117028Hz	
			);
    end component;
-----------------------------------------------------------------
	component UartRec
		Port(
			Reset       :in  std_logic;
			RCLK		:in  std_logic;
			UartIn		:in  std_logic;
			DataRec    	:out std_logic_vector(8 downto 0);
			GetData		:buffer std_logic
		    );
	end component;	
----------------------------------------------------------------
	component PCM
		Port(
			Reset		:in  std_logic;
			PCLK		:in  std_logic;
			S_Data		:in std_logic;
			FSYNC		:in std_logic;
			Slot		:in std_logic_vector(7 downto 0);--可以最大256个时隙，固定抓某个时隙
			PCM_Data	:out  std_logic_vector(7 downto 0);
			L_Data		:out  std_logic			--上升沿锁存   
		    );
	end component;
-----------------------------------------------------------------
    signal Data : std_logic_vector(8 downto 0) := (others => '0');
    signal PCM_Data : std_logic_vector(7 downto 0) := (others => '0');
    signal WrClock: std_logic := '0';
    signal S_Data	:std_logic;
    signal DioSel	:std_logic;
    signal CLK_RXD	:std_logic;
    signal CLK_TXD	:std_logic;
    signal Slot	:std_logic_vector(7 downto 0);
    signal GetDataPC	:std_logic;
    signal GetComm	:std_logic_vector(8 downto 0);
    signal UartBusy	:std_logic;--低电平时Busy
begin
------------------------------------------------------------------
u2 : UartSend
        port map (
			Reset => Reset,
			SendClk => CLK_TXD,
			Data => Data,
			Latch => WrClock,
			UartOut => Uart_Out,
			Busy => UartBusy
        			);
-------------------------------------------------------------------        
U3: BaudR
	Port map(
			Reset => Reset,
			Clock => Clock,
			CLK_RXD => CLK_RXD,
			CLK_TXD => CLK_TXD
			);
-------------------------------------------------------------------        
u4: UartRec
	Port map(
			Reset => Reset,
			RCLK => CLK_RXD,
			UartIn => Uart_In,
			DataRec => GetComm,
			GetData => GetDataPC
		    );
-------------------------------------------------------------------        
U5: PCM
	Port map(
			Reset => Reset,
			PCLK => PCM_CLK,
			S_Data => S_Data,
			FSYNC => PCM_Fsync,
			Slot => Slot,
			PCM_Data => PCM_Data,
			L_Data => WrClock
		    );
-------------------------------------------------------------------        

	with DioSel select
		S_Data <= PCM_Din when '1',
				  PCM_Dout when others;			  
----------------------------------------------------------------------
	Data <=DioSel & PCM_Data;
----------------------------------------------------------------------
	process(Reset, GetDataPC)
	begin
		if Reset = '0' then
			Slot <= "00000100"; 
			DioSel <= '1';
		elsif GetDataPC'event and GetDataPC = '1' then
			Slot <=GetComm(7 downto 0);
			DioSel <= GetComm(8);			
		end if;
	end process;
-------------------------------------------------------------------	
	
end ART_GetPcm;