pcm.vhm

PCM数据采集

--
-- Written by Synplicity
-- Product Version "Version 8.8L2"
-- Program "Synplify", Mapper "8.8.0, Build 018R"
-- Thu Jun 19 11:12:51 2008
--

--
-- Written by Synplify version 8.8.0, Build 018R
-- Thu Jun 19 11:12:51 2008
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library xp2;
use xp2.components.all;

entity PCM is
port(
  Reset :  in std_logic;
  PCLK :  in std_logic;
  S_Data :  in std_logic;
  FSYNC :  in std_logic;
  Slot : in std_logic_vector(7 downto 0);
  PCM_Data : out std_logic_vector(7 downto 0);
  L_Data :  out std_logic);
end PCM;

architecture beh of PCM is
  signal COUNT : std_logic_vector(2 downto 0);
  signal DATABUF : std_logic_vector(7 downto 0);
  signal CHUNNEL : std_logic_vector(7 downto 0);
  signal \UN7_CHUNNEL_0.DATA_TMP\ : std_logic_vector(2 downto 0);
  signal CHUNNEL_CRY : std_logic_vector(6 downto 0);
  signal CHUNNEL_S : std_logic_vector(7 downto 0);
  signal CHUNNEL_LM : std_logic_vector(7 downto 0);
  signal CHUNNEL_CRY_0_S0 : std_logic_vector(0 to 0);
  signal CHUNNEL_S_0_S1 : std_logic_vector(7 to 7);
  signal CHUNNEL_S_0_COUT : std_logic_vector(7 to 7);
  signal SLOT_C : std_logic_vector(7 downto 0);
  signal PCM_DATA_C : std_logic_vector(7 downto 0);
  signal CHUNNEL_QN : std_logic_vector(7 downto 0);
  signal COUNT_QN : std_logic_vector(2 downto 0);
  signal DATABUF_QN : std_logic_vector(7 downto 1);
  signal LASTFSYNC : std_logic ;
  signal UN1_FSYNC_0_A2 : std_logic ;
  signal I_28_0_S1 : std_logic ;
  signal UN2_CHUNNEL_0_A2 : std_logic ;
  signal COUNT_N0 : std_logic ;
  signal N_6 : std_logic ;
  signal N_10 : std_logic ;
  signal UN7_CHUNNEL_A_4_P4 : std_logic ;
  signal UN7_CHUNNEL_A_4_P7 : std_logic ;
  signal UN7_CHUNNEL_A_4_C2 : std_logic ;
  signal UN7_CHUNNEL_A_4_AC0_7 : std_logic ;
  signal UN1_FSYNC_I : std_logic ;
  signal N_15_I : std_logic ;
  signal N_12_I : std_logic ;
  signal \UN7_CHUNNEL_0.I_14_0\ : std_logic ;
  signal \UN7_CHUNNEL_0.I_23_0\ : std_logic ;
  signal \UN7_CHUNNEL_0.I_32_0\ : std_logic ;
  signal \UN7_CHUNNEL_0.I_33_0\ : std_logic ;
  signal I_1_0_S0 : std_logic ;
  signal I_1_0_S1 : std_logic ;
  signal I_10_0_S0 : std_logic ;
  signal I_10_0_S1 : std_logic ;
  signal I_28_0_S0 : std_logic ;
  signal I_28_0_COUT : std_logic ;
  signal L_DATA_1_SQMUXA_I_S_1 : std_logic ;
  signal UN7_CHUNNEL_A_4_P7_SX : std_logic ;
  signal UN7_CHUNNEL_A_4_P4_X : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal RESET_C : std_logic ;
  signal PCLK_C : std_logic ;
  signal S_DATA_C : std_logic ;
  signal FSYNC_C : std_logic ;
  signal L_DATA_C : std_logic ;
  signal LASTFSYNC_QN : std_logic ;
  signal PCLK_C_I : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  PUR_INST: PUR port map (
      PUR => VCC);
  VCC_0: VHI port map (
      Z => VCC);
  GND_0: VLO port map (
      Z => GND);
  PCLK_C_I_Z157: INV port map (
      A => PCLK_C,
      Z => PCLK_C_I);
  N_12_I <= (COUNT(1) and not COUNT(0) and not FSYNC_C) or 
	  (not COUNT(1) and COUNT(0) and not FSYNC_C) or 
	  (COUNT(1) and not COUNT(0) and LASTFSYNC) or 
	  (not COUNT(1) and COUNT(0) and LASTFSYNC);
  CHUNNEL_LM(7) <= (CHUNNEL_S(7) and not FSYNC_C) or 
	  (CHUNNEL_S(7) and LASTFSYNC);
  CHUNNEL_LM(6) <= (CHUNNEL_S(6) and not FSYNC_C) or 
	  (CHUNNEL_S(6) and LASTFSYNC);
  CHUNNEL_LM(5) <= (CHUNNEL_S(5) and not FSYNC_C) or 
	  (CHUNNEL_S(5) and LASTFSYNC);
  CHUNNEL_LM(4) <= (CHUNNEL_S(4) and not FSYNC_C) or 
	  (CHUNNEL_S(4) and LASTFSYNC);
  CHUNNEL_LM(3) <= (CHUNNEL_S(3) and not FSYNC_C) or 
	  (CHUNNEL_S(3) and LASTFSYNC);
  CHUNNEL_LM(2) <= (CHUNNEL_S(2) and not FSYNC_C) or 
	  (CHUNNEL_S(2) and LASTFSYNC);
  CHUNNEL_LM(1) <= (CHUNNEL_S(1) and not FSYNC_C) or 
	  (CHUNNEL_S(1) and LASTFSYNC);
  CHUNNEL_LM(0) <= (CHUNNEL_S(0) and not FSYNC_C) or 
	  (CHUNNEL_S(0) and LASTFSYNC);
  COUNT_N0 <= (not COUNT(0) and not FSYNC_C) or 
	  (not COUNT(0) and LASTFSYNC);
  \DATABUF_0IO[0]_REG\: IFS1P3DX port map (
      D => S_DATA_C,
      SP => UN1_FSYNC_I,
      SCLK => PCLK_C_I,
      CD => GND,
      Q => DATABUF(0));
  \PCM_DATA_0IO[0]_REG\: OFS1P3DX port map (
      D => DATABUF(0),
      SP => UN2_CHUNNEL_0_A2,
      SCLK => PCLK_C_I,
      CD => GND,
      Q => PCM_DATA_C(0));
  \PCM_DATA_0IO[1]_REG\: OFS1P3DX port map (
      D => DATABUF(1),
      SP => UN2_CHUNNEL_0_A2,
      SCLK => PCLK_C_I,
      CD => GND,
      Q => PCM_DATA_C(1));
  \PCM_DATA_0IO[2]_REG\: OFS1P3DX port map (
      D => DATABUF(2),
      SP => UN2_CHUNNEL_0_A2,
      SCLK => PCLK_C_I,
      CD => GND,
      Q => PCM_DATA_C(2));
  \PCM_DATA_0IO[3]_REG\: OFS1P3DX port map (
      D => DATABUF(3),
      SP => UN2_CHUNNEL_0_A2,
      SCLK => PCLK_C_I,
      CD => GND,
      Q => PCM_DATA_C(3));
  \PCM_DATA_0IO[4]_REG\: OFS1P3DX port map (
      D => DATABUF(4),
      SP => UN2_CHUNNEL_0_A2,
      SCLK => PCLK_C_I,
      CD => GND,
      Q => PCM_DATA_C(4));
  \PCM_DATA_0IO[5]_REG\: OFS1P3DX port map (
      D => DATABUF(5),
      SP => UN2_CHUNNEL_0_A2,
      SCLK => PCLK_C_I,
      CD => GND,
      Q => PCM_DATA_C(5));
  \PCM_DATA_0IO[6]_REG\: OFS1P3DX port map (
      D => DATABUF(6),
      SP => UN2_CHUNNEL_0_A2,
      SCLK => PCLK_C_I,
      CD => GND,
      Q => PCM_DATA_C(6));
  \PCM_DATA_0IO[7]_REG\: OFS1P3DX port map (
      D => DATABUF(7),
      SP => UN2_CHUNNEL_0_A2,
      SCLK => PCLK_C_I,
      CD => GND,
      Q => PCM_DATA_C(7));
  L_DATA_0IO_REG: OFS1P3DX port map (
      D => UN1_FSYNC_I,
      SP => N_6,
      SCLK => PCLK_C_I,
      CD => GND,
      Q => L_DATA_C);
  LASTFSYNC_REG: FD1S3AX port map (
      D => FSYNC_C,
      CK => PCLK_C_I,
      Q => LASTFSYNC);
  \DATABUF[1]_REG\: FD1P3AX port map (
      D => DATABUF(0),
      SP => UN1_FSYNC_I,
      CK => PCLK_C_I,
      Q => DATABUF(1));
  \DATABUF[2]_REG\: FD1P3AX port map (
      D => DATABUF(1),
      SP => UN1_FSYNC_I,
      CK => PCLK_C_I,
      Q => DATABUF(2));
  \DATABUF[3]_REG\: FD1P3AX port map (
      D => DATABUF(2),
      SP => UN1_FSYNC_I,
      CK => PCLK_C_I,
      Q => DATABUF(3));
  \DATABUF[4]_REG\: FD1P3AX port map (
      D => DATABUF(3),
      SP => UN1_FSYNC_I,
      CK => PCLK_C_I,
      Q => DATABUF(4));
  \DATABUF[5]_REG\: FD1P3AX port map (
      D => DATABUF(4),
      SP => UN1_FSYNC_I,
      CK => PCLK_C_I,
      Q => DATABUF(5));
  \DATABUF[6]_REG\: FD1P3AX port map (
      D => DATABUF(5),
      SP => UN1_FSYNC_I,
      CK => PCLK_C_I,
      Q => DATABUF(6));
  \DATABUF[7]_REG\: FD1P3AX port map (
      D => DATABUF(6),
      SP => UN1_FSYNC_I,
      CK => PCLK_C_I,
      Q => DATABUF(7));
  \COUNT[0]_REG\: FD1S3AX port map (
      D => COUNT_N0,
      CK => PCLK_C_I,
      Q => COUNT(0));
  \COUNT[1]_REG\: FD1S3AX port map (
      D => N_12_I,
      CK => PCLK_C_I,
      Q => COUNT(1));
  \COUNT[2]_REG\: FD1S3AX port map (
      D => N_15_I,
      CK => PCLK_C_I,
      Q => COUNT(2));
  \CHUNNEL[0]_REG\: FD1P3AX port map (
      D => CHUNNEL_LM(0),
      SP => N_10,
      CK => PCLK_C_I,
      Q => CHUNNEL(0));
  \CHUNNEL[1]_REG\: FD1P3AX port map (
      D => CHUNNEL_LM(1),
      SP => N_10,
      CK => PCLK_C_I,
      Q => CHUNNEL(1));
  \CHUNNEL[2]_REG\: FD1P3AX port map (
      D => CHUNNEL_LM(2),
      SP => N_10,
      CK => PCLK_C_I,
      Q => CHUNNEL(2));
  \CHUNNEL[3]_REG\: FD1P3AX port map (
      D => CHUNNEL_LM(3),
      SP => N_10,
      CK => PCLK_C_I,
      Q => CHUNNEL(3));
  \CHUNNEL[4]_REG\: FD1P3AX port map (
      D => CHUNNEL_LM(4),
      SP => N_10,
      CK => PCLK_C_I,
      Q => CHUNNEL(4));
  \CHUNNEL[5]_REG\: FD1P3AX port map (
      D => CHUNNEL_LM(5),
      SP => N_10,
      CK => PCLK_C_I,
      Q => CHUNNEL(5));
  \CHUNNEL[6]_REG\: FD1P3AX port map (
      D => CHUNNEL_LM(6),
      SP => N_10,
      CK => PCLK_C_I,
      Q => CHUNNEL(6));
  \CHUNNEL[7]_REG\: FD1P3AX port map (
      D => CHUNNEL_LM(7),
      SP => N_10,
      CK => PCLK_C_I,
      Q => CHUNNEL(7));
  GSR_INST: GSR port map (
      GSR => RESET_C);
  L_DATA_PAD: OB port map (
      I => L_DATA_C,
      O => L_Data);
  \PCM_DATA_PAD[7]\: OB port map (
      I => PCM_DATA_C(7),
      O => PCM_Data(7));
  \PCM_DATA_PAD[6]\: OB port map (
      I => PCM_DATA_C(6),
      O => PCM_Data(6));
  \PCM_DATA_PAD[5]\: OB port map (
      I => PCM_DATA_C(5),
      O => PCM_Data(5));
  \PCM_DATA_PAD[4]\: OB port map (
      I => PCM_DATA_C(4),
      O => PCM_Data(4));
  \PCM_DATA_PAD[3]\: OB port map (
      I => PCM_DATA_C(3),
      O => PCM_Data(3));
  \PCM_DATA_PAD[2]\: OB port map (
      I => PCM_DATA_C(2),
      O => PCM_Data(2));
  \PCM_DATA_PAD[1]\: OB port map (
      I => PCM_DATA_C(1),
      O => PCM_Data(1));
  \PCM_DATA_PAD[0]\: OB port map (
      I => PCM_DATA_C(0),
      O => PCM_Data(0));
  \SLOT_PAD[7]\: IB port map (
      I => Slot(7),
      O => SLOT_C(7));
  \SLOT_PAD[6]\: IB port map (
      I => Slot(6),
      O => SLOT_C(6));
  \SLOT_PAD[5]\: IB port map (
      I => Slot(5),
      O => SLOT_C(5));
  \SLOT_PAD[4]\: IB port map (
      I => Slot(4),
      O => SLOT_C(4));
  \SLOT_PAD[3]\: IB port map (
      I => Slot(3),
      O => SLOT_C(3));
  \SLOT_PAD[2]\: IB port map (
      I => Slot(2),
      O => SLOT_C(2));
  \SLOT_PAD[1]\: IB port map (
      I => Slot(1),
      O => SLOT_C(1));
  \SLOT_PAD[0]\: IB port map (
      I => Slot(0),
      O => SLOT_C(0));
  FSYNC_PAD: IB port map (
      I => FSYNC,
      O => FSYNC_C);
  S_DATA_PAD: IB port map (
      I => S_Data,
      O => S_DATA_C);
  PCLK_PAD: IB port map (
      I => PCLK,
      O => PCLK_C);
  RESET_PAD: IB port map (
      I => Reset,
      O => RESET_C);
  UN7_CHUNNEL_A_4_P4 <= SLOT_C(0) and SLOT_C(1) and SLOT_C(2) and SLOT_C(3);
  UN1_FSYNC_0_A2 <= FSYNC_C and not LASTFSYNC;
  UN7_CHUNNEL_A_4_C2 <= SLOT_C(0) and SLOT_C(1);
  \UN7_CHUNNEL_0.I_14_0\ <= (SLOT_C(3) and not CHUNNEL(3)) or 
	  (not SLOT_C(3) and CHUNNEL(3));
  \UN7_CHUNNEL_0.I_23_0\ <= (SLOT_C(5) and not CHUNNEL(5)) or 
	  (not SLOT_C(5) and CHUNNEL(5));
  \UN7_CHUNNEL_0.I_32_0\ <= (SLOT_C(7) and not CHUNNEL(7)) or 
	  (not SLOT_C(7) and CHUNNEL(7));
  \UN7_CHUNNEL_0.I_33_0\ <= (SLOT_C(6) and not CHUNNEL(6)) or 
	  (not SLOT_C(6) and CHUNNEL(6));
  N_10 <= (COUNT(0) and COUNT(1) and COUNT(2)) or 
	  (UN1_FSYNC_0_A2);
  UN2_CHUNNEL_0_A2 <= not COUNT(0) and not COUNT(1) and not COUNT(2) and I_28_0_S1;
  N_15_I <= (COUNT(0) and COUNT(1) and not COUNT(2) and not UN1_FSYNC_0_A2) or 
	  (not COUNT(1) and COUNT(2) and not UN1_FSYNC_0_A2) or 
	  (not COUNT(0) and COUNT(2) and not UN1_FSYNC_0_A2);
  L_DATA_1_SQMUXA_I_S_1 <= not COUNT(0) and not COUNT(1);
  N_6 <= (UN1_FSYNC_0_A2) or 
	  (L_DATA_1_SQMUXA_I_S_1 and not COUNT(2) and I_28_0_S1);
  UN7_CHUNNEL_A_4_P7_SX <= (not SLOT_C(6)) or 
	  (not SLOT_C(3)) or 
	  (not SLOT_C(2)) or 
	  (not SLOT_C(0));
  UN7_CHUNNEL_A_4_P7 <= SLOT_C(1) and SLOT_C(4) and SLOT_C(5) and not UN7_CHUNNEL_A_4_P7_SX;
  UN7_CHUNNEL_A_4_P4_X <= SLOT_C(1) and SLOT_C(2) and SLOT_C(3);
  UN7_CHUNNEL_A_4_AC0_7 <= UN7_CHUNNEL_A_4_P4_X and SLOT_C(0) and SLOT_C(4) and SLOT_C(5);
  UN1_FSYNC_I <= (not FSYNC_C) or 
	  (LASTFSYNC);
  \UN7_CHUNNEL_0.I_28_0\: CCU2B 
  generic map(
    INIT0 => "0x8241",
    INIT1 => "0x0a0c",
    INJECT1_0 => "YES",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => \UN7_CHUNNEL_0.I_32_0\,
    B0 => \UN7_CHUNNEL_0.I_33_0\,
    C0 => UN7_CHUNNEL_A_4_AC0_7,
    D0 => UN7_CHUNNEL_A_4_P7,
    A1 => GND,
    B1 => GND,
    C1 => GND,
    D1 => VCC,
    CIN => \UN7_CHUNNEL_0.DATA_TMP\(2),
    COUT => I_28_0_COUT,
    S0 => I_28_0_S0,
    S1 => I_28_0_S1);
  \UN7_CHUNNEL_0.I_10_0\: CCU2B 
  generic map(
    INIT0 => "0x2409",
    INIT1 => "0x2409",
    INJECT1_0 => "YES",
    INJECT1_1 => "YES"
  )
  port map (
    A0 => SLOT_C(2),
    B0 => CHUNNEL(2),
    C0 => \UN7_CHUNNEL_0.I_14_0\,
    D0 => UN7_CHUNNEL_A_4_C2,
    A1 => SLOT_C(4),
    B1 => CHUNNEL(4),
    C1 => \UN7_CHUNNEL_0.I_23_0\,
    D1 => UN7_CHUNNEL_A_4_P4,
    CIN => \UN7_CHUNNEL_0.DATA_TMP\(0),
    COUT => \UN7_CHUNNEL_0.DATA_TMP\(2),
    S0 => I_10_0_S0,
    S1 => I_10_0_S1);
  \UN7_CHUNNEL_0.I_1_0\: CCU2B 
  generic map(
    INIT0 => "0x0a0c",
    INIT1 => "0x4218",
    INJECT1_0 => "NO",
    INJECT1_1 => "YES"
  )
  port map (
    A0 => GND,
    B0 => VCC,
    C0 => GND,
    D0 => VCC,
    A1 => SLOT_C(0),
    B1 => SLOT_C(1),
    C1 => CHUNNEL(0),
    D1 => CHUNNEL(1),
    CIN => GND,
    COUT => \UN7_CHUNNEL_0.DATA_TMP\(0),
    S0 => I_1_0_S0,
    S1 => I_1_0_S1);
  \CHUNNEL_S_0[7]\: CCU2B 
  generic map(
    INIT0 => "0x060a",
    INIT1 => "0x0a0c",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => CHUNNEL(7),
    B0 => GND,
    C0 => GND,
    D0 => VCC,
    A1 => GND,
    B1 => GND,
    C1 => GND,
    D1 => VCC,
    CIN => CHUNNEL_CRY(6),
    COUT => CHUNNEL_S_0_COUT(7),
    S0 => CHUNNEL_S(7),
    S1 => CHUNNEL_S_0_S1(7));
  \CHUNNEL_CRY_0[5]\: CCU2B 
  generic map(
    INIT0 => "0x0600",
    INIT1 => "0x0600",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => CHUNNEL(5),
    B0 => GND,
    C0 => GND,
    D0 => VCC,
    A1 => CHUNNEL(6),
    B1 => GND,
    C1 => GND,
    D1 => VCC,
    CIN => CHUNNEL_CRY(4),
    COUT => CHUNNEL_CRY(6),
    S0 => CHUNNEL_S(5),
    S1 => CHUNNEL_S(6));
  \CHUNNEL_CRY_0[3]\: CCU2B 
  generic map(
    INIT0 => "0x0600",
    INIT1 => "0x0600",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => CHUNNEL(3),
    B0 => GND,
    C0 => GND,
    D0 => VCC,
    A1 => CHUNNEL(4),
    B1 => GND,
    C1 => GND,
    D1 => VCC,
    CIN => CHUNNEL_CRY(2),
    COUT => CHUNNEL_CRY(4),
    S0 => CHUNNEL_S(3),
    S1 => CHUNNEL_S(4));
  \CHUNNEL_CRY_0[1]\: CCU2B 
  generic map(
    INIT0 => "0x0600",
    INIT1 => "0x0600",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => CHUNNEL(1),
    B0 => GND,
    C0 => GND,
    D0 => VCC,
    A1 => CHUNNEL(2),
    B1 => GND,
    C1 => GND,
    D1 => VCC,
    CIN => CHUNNEL_CRY(0),
    COUT => CHUNNEL_CRY(2),
    S0 => CHUNNEL_S(1),
    S1 => CHUNNEL_S(2));
  \CHUNNEL_CRY_0[0]\: CCU2B 
  generic map(
    INIT0 => "0x0a0c",
    INIT1 => "0x0600",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => GND,
    B0 => VCC,
    C0 => GND,
    D0 => VCC,
    A1 => CHUNNEL(0),
    B1 => GND,
    C1 => GND,
    D1 => VCC,
    CIN => GND,
    COUT => CHUNNEL_CRY(0),
    S0 => CHUNNEL_CRY_0_S0(0),
    S1 => CHUNNEL_S(0));
  NN_1 <= '0';
  NN_2 <= '1';
end beh;