uartrec.log

PCM数据采集

#Build: Synplify for Lattice 8.8L2, Build 008R, Dec  7 2006
#install: D:\ISPTOOLS7_0\SYNPBASE
#OS: Windows XP 5.1
#Hostname: STAR-PANCAT

#Implementation: getpcm

#Thu Jun 19 11:45:53 2008

$ Start of Compile
#Thu Jun 19 11:45:53 2008

Synplicity VHDL Compiler, version 3.7.5, Build 159R, built Apr 13 2007
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved

@N: CD720 :"D:\ISPTOOLS7_0\SYNPBASE\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"D:\cpld\fpga\getpcm\uartrec.vhd":6:7:6:13|Top entity is set to UartRec.
VHDL syntax check successful!
@N: CD630 :"D:\cpld\fpga\getpcm\uartrec.vhd":6:7:6:13|Synthesizing work.uartrec.atr_uartrec 
Post processing for work.uartrec.atr_uartrec
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jun 19 11:45:53 2008

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Synplicity Generic Technology Mapper, Version 8.8.0, Build 018R, Built Apr 17 2007 19:29:01
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved
Product Version Version 8.8L2
@N: MF249 |Running in 32-bit mode.


RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Clock Buffers:
  Inserting Clock buffer for port RCLK,	TNM=RCLK
  Inserting Clock buffer for port UartIn,	TNM=UartIn


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 51MB)

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		     0.69ns		  23 /        26
   2		0h:00m:00s		     0.69ns		  23 /        26
   3		0h:00m:00s		     0.69ns		  23 /        26
------------------------------------------------------------

Net buffering Report for view:work.UartRec(atr_uartrec):
No nets needed buffering.


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)
Found clock UartRec|RCLK with period 5.00ns 
Found clock UartRec|UartIn with period 5.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Jun 19 11:45:54 2008
#


Top view:               UartRec
Requested Frequency:    200.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..


Performance Summary 
*******************


Worst slack in design: 0.692

                   Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack     Type         Group              
---------------------------------------------------------------------------------------------------------------------
UartRec|RCLK       200.0 MHz     232.1 MHz     5.000         4.308         0.692     inferred     Inferred_clkgroup_1
System             200.0 MHz     470.7 MHz     5.000         2.125         2.875     system       default_clkgroup   
=====================================================================================================================





Clock Relationships
*******************

Clocks                        |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------
Starting        Ending        |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------------------
UartRec|UartIn  UartRec|RCLK  |  No paths    -      |  No paths    -      |  No paths    -      |  Diff grp    -    
UartRec|RCLK    UartRec|RCLK  |  5.000       0.692  |  No paths    -      |  No paths    -      |  No paths    -    
====================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port       Starting            User           Arrival     Required          
Name       Reference           Constraint     Time        Time         Slack
           Clock                                                            
----------------------------------------------------------------------------
RCLK       NA                  NA             NA          NA           NA   
Reset      System (rising)     NA             0.000       2.875             
UartIn     System (rising)     NA             0.000       3.068             
============================================================================


Output Ports: 

Port           Starting                  User           Arrival     Required          
Name           Reference                 Constraint     Time        Time         Slack
               Clock                                                                  
--------------------------------------------------------------------------------------
DataRec[0]     UartRec|RCLK (rising)     NA             4.187       5.000             
DataRec[1]     UartRec|RCLK (rising)     NA             4.187       5.000             
DataRec[2]     UartRec|RCLK (rising)     NA             4.187       5.000             
DataRec[3]     UartRec|RCLK (rising)     NA             4.187       5.000             
DataRec[4]     UartRec|RCLK (rising)     NA             4.187       5.000             
DataRec[5]     UartRec|RCLK (rising)     NA             4.187       5.000             
DataRec[6]     UartRec|RCLK (rising)     NA             4.187       5.000             
DataRec[7]     UartRec|RCLK (rising)     NA             4.187       5.000             
DataRec[8]     UartRec|RCLK (rising)     NA             4.187       5.000             
GetData        UartRec|RCLK (rising)     NA             4.234       5.000             
======================================================================================


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report
Part: lfxp2_17e-5

Register bits: 26 of 16560 (0%)
I/O cells:       13

Details:
FD1P3AX:        9
FD1P3AY:        1
FD1S3AX:        6
FD1S3DX:        1
GSR:            1
IB:             3
INV:            3
OB:             10
OFS1P3DX:       9
ORCALUT4:       18
VHI:            1
VLO:            1

Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)
Writing Analyst data base D:\cpld\fpga\getpcm\UartRec.srm
@N: MF203 |Set autoconstraint_io 
Writing EDIF Netlist and constraint files
@N: MF203 |Set autoconstraint_io 
Version 8.8L2
Writing Verilog Simulation files
@N: MF203 |Set autoconstraint_io 
Writing VHDL Simulation files
@N: MF203 |Set autoconstraint_io 
@N: MF203 |Set autoconstraint_io 
Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jun 19 11:45:55 2008

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