uartsend.vhm

PCM数据采集

--
-- Written by Synplicity
-- Product Version "Version 8.8L2"
-- Program "Synplify", Mapper "8.8.0, Build 018R"
-- Thu Jun 19 21:20:44 2008
--

--
-- Written by Synplify version 8.8.0, Build 018R
-- Thu Jun 19 21:20:44 2008
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library machxo;
use machxo.components.all;

entity UartSend is
port(
  Reset :  in std_logic;
  SendClk :  in std_logic;
  Data : in std_logic_vector(8 downto 0);
  Latch :  in std_logic;
  UartOut :  out std_logic;
  Busy :  out std_logic);
end UartSend;

architecture beh of UartSend is
  signal TSTATE : std_logic_vector(3 downto 0);
  signal SENDBUFFER : std_logic_vector(8 downto 0);
  signal SENDBUFFER_4 : std_logic_vector(7 downto 0);
  signal DATA_C : std_logic_vector(8 downto 0);
  signal SENDBUFFER_QN : std_logic_vector(8 downto 0);
  signal TSTATE_QN : std_logic_vector(3 downto 0);
  signal START : std_logic ;
  signal UARTOUT_2 : std_logic ;
  signal TSTATE_N1 : std_logic ;
  signal TSTATE_N2 : std_logic ;
  signal TSTATE_N3 : std_logic ;
  signal UN1_TSTATE_1 : std_logic ;
  signal N_8 : std_logic ;
  signal N_34_I : std_logic ;
  signal N_36_I : std_logic ;
  signal N_6_I : std_logic ;
  signal N_30_I : std_logic ;
  signal UARTOUT7_I : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal RESET_C : std_logic ;
  signal SENDCLK_C : std_logic ;
  signal LATCH_C : std_logic ;
  signal UARTOUT_C : std_logic ;
  signal BUSY_C : std_logic ;
  signal SENDCOMP_QN : std_logic ;
  signal START_QN : std_logic ;
  signal UARTOUT_QN : std_logic ;
  signal START_I : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  PUR_INST: PUR port map (
      PUR => VCC);
  VCC_0: VHI port map (
      Z => VCC);
  GND_0: VLO port map (
      Z => GND);
  START_I_Z92: INV port map (
      A => START,
      Z => START_I);
  N_34_I <= (START) or 
	  (TSTATE(3)) or 
	  (TSTATE(2)) or 
	  (TSTATE(1));
  UARTOUT7_I <= (not TSTATE(3) and not TSTATE(2) and not TSTATE(1)) or 
	  (START);
  TSTATE_N2 <= (TSTATE(2) and not TSTATE(0)) or 
	  (START) or 
	  (TSTATE(2) and not TSTATE(1)) or 
	  (not TSTATE(2) and TSTATE(1) and TSTATE(0));
  \TSTATE[0]_REG\: FD1P3AX port map (
      D => N_6_I,
      SP => N_34_I,
      CK => SENDCLK_C,
      Q => TSTATE(0));
  \TSTATE[1]_REG\: FD1P3AX port map (
      D => TSTATE_N1,
      SP => N_34_I,
      CK => SENDCLK_C,
      Q => TSTATE(1));
  \TSTATE[2]_REG\: FD1P3AX port map (
      D => TSTATE_N2,
      SP => N_34_I,
      CK => SENDCLK_C,
      Q => TSTATE(2));
  \TSTATE[3]_REG\: FD1P3AX port map (
      D => TSTATE_N3,
      SP => N_34_I,
      CK => SENDCLK_C,
      Q => TSTATE(3));
  \SENDBUFFER[0]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(0),
      SP => N_34_I,
      CK => SENDCLK_C,
      Q => SENDBUFFER(0));
  \SENDBUFFER[1]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(1),
      SP => N_34_I,
      CK => SENDCLK_C,
      Q => SENDBUFFER(1));
  \SENDBUFFER[2]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(2),
      SP => N_34_I,
      CK => SENDCLK_C,
      Q => SENDBUFFER(2));
  \SENDBUFFER[3]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(3),
      SP => N_34_I,
      CK => SENDCLK_C,
      Q => SENDBUFFER(3));
  \SENDBUFFER[4]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(4),
      SP => N_34_I,
      CK => SENDCLK_C,
      Q => SENDBUFFER(4));
  \SENDBUFFER[5]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(5),
      SP => N_34_I,
      CK => SENDCLK_C,
      Q => SENDBUFFER(5));
  \SENDBUFFER[6]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(6),
      SP => N_34_I,
      CK => SENDCLK_C,
      Q => SENDBUFFER(6));
  \SENDBUFFER[7]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(7),
      SP => N_34_I,
      CK => SENDCLK_C,
      Q => SENDBUFFER(7));
  \SENDBUFFER[8]_REG\: FD1P3AX port map (
      D => N_30_I,
      SP => N_34_I,
      CK => SENDCLK_C,
      Q => SENDBUFFER(8));
  UARTOUT_REG: FD1S3AY port map (
      D => UARTOUT_2,
      CK => SENDCLK_C,
      Q => UARTOUT_C);
  START_REG: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => VCC,
    CK => LATCH_C,
    CD => N_36_I,
    Q => START);
  SENDCOMP_REG: FD1P3AY port map (
      D => START_I,
      SP => UARTOUT7_I,
      CK => SENDCLK_C,
      Q => BUSY_C);
  GSR_INST: GSR port map (
      GSR => RESET_C);
  BUSY_PAD: OB port map (
      I => BUSY_C,
      O => Busy);
  UARTOUT_PAD: OB port map (
      I => UARTOUT_C,
      O => UartOut);
  LATCH_PAD: IB port map (
      I => Latch,
      O => LATCH_C);
  \DATA_PAD[8]\: IB port map (
      I => Data(8),
      O => DATA_C(8));
  \DATA_PAD[7]\: IB port map (
      I => Data(7),
      O => DATA_C(7));
  \DATA_PAD[6]\: IB port map (
      I => Data(6),
      O => DATA_C(6));
  \DATA_PAD[5]\: IB port map (
      I => Data(5),
      O => DATA_C(5));
  \DATA_PAD[4]\: IB port map (
      I => Data(4),
      O => DATA_C(4));
  \DATA_PAD[3]\: IB port map (
      I => Data(3),
      O => DATA_C(3));
  \DATA_PAD[2]\: IB port map (
      I => Data(2),
      O => DATA_C(2));
  \DATA_PAD[1]\: IB port map (
      I => Data(1),
      O => DATA_C(1));
  \DATA_PAD[0]\: IB port map (
      I => Data(0),
      O => DATA_C(0));
  SENDCLK_PAD: IB port map (
      I => SendClk,
      O => SENDCLK_C);
  RESET_PAD: IB port map (
      I => Reset,
      O => RESET_C);
  SENDBUFFER_4(7) <= (DATA_C(7) and START) or 
	  (not START and SENDBUFFER(8));
  SENDBUFFER_4(6) <= (DATA_C(6) and START) or 
	  (not START and SENDBUFFER(7));
  SENDBUFFER_4(5) <= (DATA_C(5) and START) or 
	  (not START and SENDBUFFER(6));
  SENDBUFFER_4(4) <= (DATA_C(4) and START) or 
	  (not START and SENDBUFFER(5));
  SENDBUFFER_4(3) <= (DATA_C(3) and START) or 
	  (not START and SENDBUFFER(4));
  SENDBUFFER_4(2) <= (DATA_C(2) and START) or 
	  (not START and SENDBUFFER(3));
  SENDBUFFER_4(1) <= (DATA_C(1) and START) or 
	  (not START and SENDBUFFER(2));
  SENDBUFFER_4(0) <= (DATA_C(0) and START) or 
	  (not START and SENDBUFFER(1));
  N_30_I <= (not START) or 
	  (DATA_C(8));
  N_6_I <= (not TSTATE(0)) or 
	  (START);
  N_36_I <= (not BUSY_C) or 
	  (not RESET_C);
  TSTATE_N1 <= (START) or 
	  (TSTATE(0) and not TSTATE(1)) or 
	  (not TSTATE(0) and TSTATE(1));
  UN1_TSTATE_1 <= not TSTATE(1) and not TSTATE(2) and not TSTATE(3);
  N_8 <= not START and TSTATE(0) and TSTATE(1);
  TSTATE_N3 <= (N_8 and TSTATE(2) and not TSTATE(3)) or 
	  (not START and not TSTATE(2) and TSTATE(3)) or 
	  (not N_8 and not START and TSTATE(3)) or 
	  (N_8 and START and TSTATE(2));
  UARTOUT_2 <= (not START and SENDBUFFER(0)) or 
	  (not START and UN1_TSTATE_1);
  NN_1 <= '0';
  NN_2 <= '1';
  TSALL_INST: TSALL port map (
      TSALL => NN_1);
end beh;