getpcm.vhm

PCM数据采集

  Reset_c :  in std_logic;
  CLK_TXD :  in std_logic);
end UartSend;

architecture beh of UartSend is
  signal TSTATE : std_logic_vector(3 downto 0);
  signal TSTATE_QN : std_logic_vector(3 downto 0);
  signal SENDBUFFER_4 : std_logic_vector(7 downto 0);
  signal SENDBUFFER : std_logic_vector(8 downto 0);
  signal SENDBUFFER_QN : std_logic_vector(8 downto 0);
  signal START : std_logic ;
  signal START_I : std_logic ;
  signal N_34_I : std_logic ;
  signal SENDBUFFER10_I : std_logic ;
  signal TSTATE_N2 : std_logic ;
  signal N_6_I : std_logic ;
  signal TSTATE_N1 : std_logic ;
  signal TSTATE_N3 : std_logic ;
  signal N_30_I : std_logic ;
  signal UARTOUT_2 : std_logic ;
  signal UARTOUT_QN : std_logic ;
  signal N_36_I : std_logic ;
  signal START_QN_0 : std_logic ;
  signal UARTBUSY : std_logic ;
  signal SENDCOMP_QN : std_logic ;
  signal UN1_TSTATE_1 : std_logic ;
  signal N_8 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  START_I_Z74: INV port map (
      A => START,
      Z => START_I);
  N_34_I <= (START) or 
	  (TSTATE(3)) or 
	  (TSTATE(2)) or 
	  (TSTATE(1));
  SENDBUFFER10_I <= (not TSTATE(3) and not TSTATE(2) and not TSTATE(1)) or 
	  (START);
  TSTATE_N2 <= (TSTATE(2) and not TSTATE(0)) or 
	  (START) or 
	  (TSTATE(2) and not TSTATE(1)) or 
	  (not TSTATE(2) and TSTATE(1) and TSTATE(0));
  \TSTATE[0]_REG\: FD1P3AX port map (
      D => N_6_I,
      SP => N_34_I,
      CK => CLK_TXD,
      Q => TSTATE(0));
  \TSTATE[1]_REG\: FD1P3AX port map (
      D => TSTATE_N1,
      SP => N_34_I,
      CK => CLK_TXD,
      Q => TSTATE(1));
  \TSTATE[2]_REG\: FD1P3AX port map (
      D => TSTATE_N2,
      SP => N_34_I,
      CK => CLK_TXD,
      Q => TSTATE(2));
  \TSTATE[3]_REG\: FD1P3AX port map (
      D => TSTATE_N3,
      SP => N_34_I,
      CK => CLK_TXD,
      Q => TSTATE(3));
  \SENDBUFFER[0]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(0),
      SP => N_34_I,
      CK => CLK_TXD,
      Q => SENDBUFFER(0));
  \SENDBUFFER[1]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(1),
      SP => N_34_I,
      CK => CLK_TXD,
      Q => SENDBUFFER(1));
  \SENDBUFFER[2]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(2),
      SP => N_34_I,
      CK => CLK_TXD,
      Q => SENDBUFFER(2));
  \SENDBUFFER[3]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(3),
      SP => N_34_I,
      CK => CLK_TXD,
      Q => SENDBUFFER(3));
  \SENDBUFFER[4]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(4),
      SP => N_34_I,
      CK => CLK_TXD,
      Q => SENDBUFFER(4));
  \SENDBUFFER[5]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(5),
      SP => N_34_I,
      CK => CLK_TXD,
      Q => SENDBUFFER(5));
  \SENDBUFFER[6]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(6),
      SP => N_34_I,
      CK => CLK_TXD,
      Q => SENDBUFFER(6));
  \SENDBUFFER[7]_REG\: FD1P3AX port map (
      D => SENDBUFFER_4(7),
      SP => N_34_I,
      CK => CLK_TXD,
      Q => SENDBUFFER(7));
  \SENDBUFFER[8]_REG\: FD1P3AX port map (
      D => N_30_I,
      SP => N_34_I,
      CK => CLK_TXD,
      Q => SENDBUFFER(8));
  UARTOUT_REG: FD1S3AY port map (
      D => UARTOUT_2,
      CK => CLK_TXD,
      Q => Uart_Out_c);
  START_REG: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => VCC,
    CK => WrClock,
    CD => N_36_I,
    Q => START);
  SENDCOMP_REG: FD1P3AY port map (
      D => START_I,
      SP => SENDBUFFER10_I,
      CK => CLK_TXD,
      Q => UARTBUSY);
  SENDBUFFER_4(7) <= (PCM_Data(7) and START) or 
	  (not START and SENDBUFFER(8));
  SENDBUFFER_4(6) <= (PCM_Data(6) and START) or 
	  (not START and SENDBUFFER(7));
  SENDBUFFER_4(5) <= (PCM_Data(5) and START) or 
	  (not START and SENDBUFFER(6));
  SENDBUFFER_4(4) <= (PCM_Data(4) and START) or 
	  (not START and SENDBUFFER(5));
  SENDBUFFER_4(3) <= (PCM_Data(3) and START) or 
	  (not START and SENDBUFFER(4));
  SENDBUFFER_4(2) <= (PCM_Data(2) and START) or 
	  (not START and SENDBUFFER(3));
  SENDBUFFER_4(1) <= (PCM_Data(1) and START) or 
	  (not START and SENDBUFFER(2));
  SENDBUFFER_4(0) <= (PCM_Data(0) and START) or 
	  (not START and SENDBUFFER(1));
  N_30_I <= (not START) or 
	  (DioSel);
  N_6_I <= (not TSTATE(0)) or 
	  (START);
  N_36_I <= (not UARTBUSY) or 
	  (not Reset_c);
  TSTATE_N1 <= (START) or 
	  (TSTATE(0) and not TSTATE(1)) or 
	  (not TSTATE(0) and TSTATE(1));
  UN1_TSTATE_1 <= not TSTATE(1) and not TSTATE(2) and not TSTATE(3);
  N_8 <= not START and TSTATE(0) and TSTATE(1);
  TSTATE_N3 <= (N_8 and TSTATE(2) and not TSTATE(3)) or 
	  (not START and not TSTATE(2) and TSTATE(3)) or 
	  (not N_8 and not START and TSTATE(3)) or 
	  (N_8 and START and TSTATE(2));
  UARTOUT_2 <= (not START and SENDBUFFER(0)) or 
	  (not START and UN1_TSTATE_1);
  NN_1 <= '0';
  NN_2 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library machxo;
use machxo.components.all;

entity GetPcm is
port(
  Reset :  in std_logic;
  Clock :  in std_logic;
  Uart_In :  in std_logic;
  Uart_Out :  out std_logic;
  Slot_LED : out std_logic_vector(7 downto 0);
  DioSel_LED :  out std_logic;
  PCM_CLK :  in std_logic;
  PCM_Fsync :  in std_logic;
  PCM_Din :  in std_logic;
  PCM_Dout :  in std_logic);
end GetPcm;

architecture beh of GetPcm is
  signal PCM_DATA : std_logic_vector(7 downto 0);
  signal GETCOMM : std_logic_vector(8 downto 0);
  signal SLOT : std_logic_vector(7 downto 0);
  signal SLOT_QN : std_logic_vector(7 downto 0);
  signal CLK_TXD : std_logic ;
  signal WRCLOCK : std_logic ;
  signal GETDATAPC : std_logic ;
  signal S_DATA : std_logic ;
  signal DIOSEL : std_logic ;
  signal CLK_RXD : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal RESET_C : std_logic ;
  signal CLOCK_C : std_logic ;
  signal UART_IN_C : std_logic ;
  signal UART_OUT_C : std_logic ;
  signal PCM_CLK_C : std_logic ;
  signal PCM_FSYNC_C : std_logic ;
  signal PCM_DIN_C : std_logic ;
  signal PCM_DOUT_C : std_logic ;
  signal DIOSEL_QN : std_logic ;
  signal PCM_CLK_C_I : std_logic ;
  signal UART_IN_C_I : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component UartSend
    port(
      PCM_Data : in std_logic_vector(7 downto 0);
      DioSel :  in std_logic;
      GND :  in std_logic;
      WrClock :  in std_logic;
      VCC :  in std_logic;
      Uart_Out_c :  out std_logic;
      Reset_c :  in std_logic;
      CLK_TXD :  in std_logic  );
  end component;
  component BaudR
    port(
      GND :  in std_logic;
      CLK_TXD :  out std_logic;
      Clock_c :  in std_logic;
      Reset_c :  in std_logic;
      CLK_RXD :  out std_logic  );
  end component;
  component UartRec
    port(
      GetComm : out std_logic_vector(8 downto 0);
      Uart_In_c_i :  in std_logic;
      VCC :  in std_logic;
      Uart_In_c :  in std_logic;
      Reset_c :  in std_logic;
      CLK_RXD :  in std_logic;
      GND :  in std_logic;
      GetDataPC :  out std_logic  );
  end component;
  component PCM
    port(
      PCM_Data : out std_logic_vector(7 downto 0);
      Slot : in std_logic_vector(7 downto 0);
      WrClock :  out std_logic;
      VCC :  in std_logic;
      Reset_c :  in std_logic;
      PCM_CLK_c_i :  in std_logic;
      S_Data :  in std_logic;
      GND :  in std_logic;
      PCM_Fsync_c :  in std_logic  );
  end component;
begin
  PUR_INST: PUR port map (
      PUR => VCC);
  GND_0: VLO port map (
      Z => GND);
  VCC_0: VHI port map (
      Z => VCC);
  UART_IN_C_I_Z79: INV port map (
      A => UART_IN_C,
      Z => UART_IN_C_I);
  PCM_CLK_C_I_Z80: INV port map (
      A => PCM_CLK_C,
      Z => PCM_CLK_C_I);
  \SLOT[0]_REG\: FD1S3AX port map (
      D => GETCOMM(0),
      CK => GETDATAPC,
      Q => SLOT(0));
  \SLOT[1]_REG\: FD1S3AX port map (
      D => GETCOMM(1),
      CK => GETDATAPC,
      Q => SLOT(1));
  \SLOT[2]_REG\: FD1S3AX port map (
      D => GETCOMM(2),
      CK => GETDATAPC,
      Q => SLOT(2));
  \SLOT[3]_REG\: FD1S3AX port map (
      D => GETCOMM(3),
      CK => GETDATAPC,
      Q => SLOT(3));
  \SLOT[4]_REG\: FD1S3AX port map (
      D => GETCOMM(4),
      CK => GETDATAPC,
      Q => SLOT(4));
  \SLOT[5]_REG\: FD1S3AX port map (
      D => GETCOMM(5),
      CK => GETDATAPC,
      Q => SLOT(5));
  \SLOT[6]_REG\: FD1S3AX port map (
      D => GETCOMM(6),
      CK => GETDATAPC,
      Q => SLOT(6));
  \SLOT[7]_REG\: FD1S3AX port map (
      D => GETCOMM(7),
      CK => GETDATAPC,
      Q => SLOT(7));
  DIOSEL_REG: FD1S3AX port map (
      D => GETCOMM(8),
      CK => GETDATAPC,
      Q => DIOSEL);
  GSR_INST: GSR port map (
      GSR => RESET_C);
  PCM_DOUT_PAD: IB port map (
      I => PCM_Dout,
      O => PCM_DOUT_C);
  PCM_DIN_PAD: IB port map (
      I => PCM_Din,
      O => PCM_DIN_C);
  PCM_FSYNC_PAD: IB port map (
      I => PCM_Fsync,
      O => PCM_FSYNC_C);
  PCM_CLK_PAD: IB port map (
      I => PCM_CLK,
      O => PCM_CLK_C);
  DIOSEL_LED_PAD: OB port map (
      I => DIOSEL,
      O => DioSel_LED);
  \SLOT_LED_PAD[7]\: OB port map (
      I => SLOT(7),
      O => Slot_LED(7));
  \SLOT_LED_PAD[6]\: OB port map (
      I => SLOT(6),
      O => Slot_LED(6));
  \SLOT_LED_PAD[5]\: OB port map (
      I => SLOT(5),
      O => Slot_LED(5));
  \SLOT_LED_PAD[4]\: OB port map (
      I => SLOT(4),
      O => Slot_LED(4));
  \SLOT_LED_PAD[3]\: OB port map (
      I => SLOT(3),
      O => Slot_LED(3));
  \SLOT_LED_PAD[2]\: OB port map (
      I => SLOT(2),
      O => Slot_LED(2));
  \SLOT_LED_PAD[1]\: OB port map (
      I => SLOT(1),
      O => Slot_LED(1));
  \SLOT_LED_PAD[0]\: OB port map (
      I => SLOT(0),
      O => Slot_LED(0));
  UART_OUT_PAD: OB port map (
      I => UART_OUT_C,
      O => Uart_Out);
  UART_IN_PAD: IB port map (
      I => Uart_In,
      O => UART_IN_C);
  CLOCK_PAD: IB port map (
      I => Clock,
      O => CLOCK_C);
  RESET_PAD: IB port map (
      I => Reset,
      O => RESET_C);
  S_DATA <= (DIOSEL and PCM_DIN_C) or 
	  (not DIOSEL and PCM_DOUT_C);
  U2: UartSend port map (
      PCM_Data(0) => PCM_DATA(0),
      PCM_Data(1) => PCM_DATA(1),
      PCM_Data(2) => PCM_DATA(2),
      PCM_Data(3) => PCM_DATA(3),
      PCM_Data(4) => PCM_DATA(4),
      PCM_Data(5) => PCM_DATA(5),
      PCM_Data(6) => PCM_DATA(6),
      PCM_Data(7) => PCM_DATA(7),
      DioSel => DIOSEL,
      GND => GND,
      WrClock => WRCLOCK,
      VCC => VCC,
      Uart_Out_c => UART_OUT_C,
      Reset_c => RESET_C,
      CLK_TXD => CLK_TXD);
  U3: BaudR port map (
      GND => GND,
      CLK_TXD => CLK_TXD,
      Clock_c => CLOCK_C,
      Reset_c => RESET_C,
      CLK_RXD => CLK_RXD);
  U4: UartRec port map (
      GetComm(0) => GETCOMM(0),
      GetComm(1) => GETCOMM(1),
      GetComm(2) => GETCOMM(2),
      GetComm(3) => GETCOMM(3),
      GetComm(4) => GETCOMM(4),
      GetComm(5) => GETCOMM(5),
      GetComm(6) => GETCOMM(6),
      GetComm(7) => GETCOMM(7),
      GetComm(8) => GETCOMM(8),
      Uart_In_c_i => UART_IN_C_I,
      VCC => VCC,
      Uart_In_c => UART_IN_C,
      Reset_c => RESET_C,
      CLK_RXD => CLK_RXD,
      GND => GND,
      GetDataPC => GETDATAPC);
  U5: PCM port map (
      PCM_Data(0) => PCM_DATA(0),
      PCM_Data(1) => PCM_DATA(1),
      PCM_Data(2) => PCM_DATA(2),
      PCM_Data(3) => PCM_DATA(3),
      PCM_Data(4) => PCM_DATA(4),
      PCM_Data(5) => PCM_DATA(5),
      PCM_Data(6) => PCM_DATA(6),
      PCM_Data(7) => PCM_DATA(7),
      Slot(0) => SLOT(0),
      Slot(1) => SLOT(1),
      Slot(2) => SLOT(2),
      Slot(3) => SLOT(3),
      Slot(4) => SLOT(4),
      Slot(5) => SLOT(5),
      Slot(6) => SLOT(6),
      Slot(7) => SLOT(7),
      WrClock => WRCLOCK,
      VCC => VCC,
      Reset_c => RESET_C,
      PCM_CLK_c_i => PCM_CLK_C_I,
      S_Data => S_DATA,
      GND => GND,
      PCM_Fsync_c => PCM_FSYNC_C);
  NN_1 <= '0';
  NN_2 <= '1';
  TSALL_INST: TSALL port map (
      TSALL => NN_1);
end beh;