getpcm.vhm

PCM数据采集

    CIN => UN16_CHUNNEL_A_4_CRY_5,
    COUT0 => UN16_CHUNNEL_A_4_CRY_6,
    COUT1 => UN16_CHUNNEL_A_4_CRY_6_0_COUT1,
    S0 => UN16_CHUNNEL_A_4(6),
    S1 => UN16_CHUNNEL_A_4(7));
  UN16_CHUNNEL_A_4_CRY_4_0: CCU2 
  generic map(
    INIT0 => "0x300a",
    INIT1 => "0x300a",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => Slot(4),
    B0 => GND,
    C0 => GND,
    D0 => GND,
    A1 => Slot(5),
    B1 => GND,
    C1 => GND,
    D1 => GND,
    CIN => UN16_CHUNNEL_A_4_CRY_3,
    COUT0 => UN16_CHUNNEL_A_4_CRY_4,
    COUT1 => UN16_CHUNNEL_A_4_CRY_5,
    S0 => UN16_CHUNNEL_A_4(4),
    S1 => UN16_CHUNNEL_A_4(5));
  UN16_CHUNNEL_A_4_CRY_2_0: CCU2 
  generic map(
    INIT0 => "0x300a",
    INIT1 => "0x300a",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => Slot(2),
    B0 => GND,
    C0 => GND,
    D0 => GND,
    A1 => Slot(3),
    B1 => GND,
    C1 => GND,
    D1 => GND,
    CIN => UN16_CHUNNEL_A_4_CRY_1,
    COUT0 => UN16_CHUNNEL_A_4_CRY_2,
    COUT1 => UN16_CHUNNEL_A_4_CRY_3,
    S0 => UN16_CHUNNEL_A_4(2),
    S1 => UN16_CHUNNEL_A_4(3));
  UN16_CHUNNEL_A_4_CRY_0_0: CCU2 
  generic map(
    INIT0 => "0x300a",
    INIT1 => "0x300a",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => Slot(0),
    B0 => GND,
    C0 => GND,
    D0 => GND,
    A1 => Slot(1),
    B1 => GND,
    C1 => GND,
    D1 => GND,
    CIN => VCC,
    COUT0 => UN16_CHUNNEL_A_4_CRY_0,
    COUT1 => UN16_CHUNNEL_A_4_CRY_1,
    S0 => UN16_CHUNNEL_A_4_CRY_0_0_S0,
    S1 => UN16_CHUNNEL_A_4(1));
  WrClock <= L_DATA_I;
  NN_1 <= '0';
  NN_2 <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library machxo;
use machxo.components.all;

entity UartRec is
port(
  GetComm : out std_logic_vector(8 downto 0);
  Uart_In_c_i :  in std_logic;
  VCC :  in std_logic;
  Uart_In_c :  in std_logic;
  Reset_c :  in std_logic;
  CLK_RXD :  in std_logic;
  GND :  in std_logic;
  GetDataPC :  out std_logic);
end UartRec;

architecture beh of UartRec is
  signal RSTATE : std_logic_vector(5 downto 0);
  signal RSTATE_3 : std_logic_vector(5 downto 0);
  signal RSTATE_5 : std_logic_vector(0 to 0);
  signal RSTATE_QN : std_logic_vector(5 downto 0);
  signal RECBUFFER : std_logic_vector(8 downto 0);
  signal RECBUFFER_QN : std_logic_vector(8 downto 0);
  signal DATAREC_QN : std_logic_vector(8 downto 0);
  signal GETDATAPC_I : std_logic ;
  signal START : std_logic ;
  signal START_I : std_logic ;
  signal UN23_RSTATE_P4 : std_logic ;
  signal UN23_RSTATE_AXBXC5 : std_logic ;
  signal UN23_RSTATE_AXBXC2 : std_logic ;
  signal UN23_RSTATE_AXBXC1 : std_logic ;
  signal UN8_RSTATE : std_logic ;
  signal UN23_RSTATE_AXBXC3 : std_logic ;
  signal UN23_RSTATE_AXBXC4 : std_logic ;
  signal START_QN : std_logic ;
  signal N_23_I : std_logic ;
  signal GETDATA_I : std_logic ;
  signal GETDATA_QN : std_logic ;
  signal UN13_RSTATE : std_logic ;
  signal UN18_RSTATE_1 : std_logic ;
  signal UN1_RSTATE_2_1 : std_logic ;
  signal UN13_RSTATE_0 : std_logic ;
  signal GETDATAPC_INT_7 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  GETDATAPC_I_Z90: INV port map (
      A => GETDATAPC_INT_7,
      Z => GETDATAPC_I);
  START_I_Z91: INV port map (
      A => START,
      Z => START_I);
  UN23_RSTATE_AXBXC5 <= (UN23_RSTATE_P4 and RSTATE(4) and not RSTATE(5)) or 
	  (UN23_RSTATE_P4 and START) or 
	  (not RSTATE(4) and not START and RSTATE(5)) or 
	  (not UN23_RSTATE_P4 and not START and RSTATE(5));
  UN23_RSTATE_AXBXC2 <= (RSTATE_3(1) and RSTATE_3(0) and not RSTATE(2)) or 
	  (not RSTATE_3(0) and RSTATE(2) and not START) or 
	  (not RSTATE_3(1) and RSTATE(2) and not START) or 
	  (RSTATE_3(1) and RSTATE_3(0) and START);
  UN23_RSTATE_AXBXC1 <= (RSTATE_3(0) and not RSTATE(1)) or 
	  (not RSTATE_3(0) and RSTATE(1) and not START) or 
	  (RSTATE_3(0) and START);
  UN8_RSTATE <= not RSTATE(1) and RSTATE(0) and not START;
  \RSTATE[0]_REG\: FD1S3AX port map (
      D => RSTATE_5(0),
      CK => CLK_RXD,
      Q => RSTATE(0));
  \RSTATE[1]_REG\: FD1S3AX port map (
      D => UN23_RSTATE_AXBXC1,
      CK => CLK_RXD,
      Q => RSTATE(1));
  \RSTATE[2]_REG\: FD1S3AX port map (
      D => UN23_RSTATE_AXBXC2,
      CK => CLK_RXD,
      Q => RSTATE(2));
  \RSTATE[3]_REG\: FD1S3AX port map (
      D => UN23_RSTATE_AXBXC3,
      CK => CLK_RXD,
      Q => RSTATE(3));
  \RSTATE[4]_REG\: FD1S3AX port map (
      D => UN23_RSTATE_AXBXC4,
      CK => CLK_RXD,
      Q => RSTATE(4));
  \RSTATE[5]_REG\: FD1S3AX port map (
      D => UN23_RSTATE_AXBXC5,
      CK => CLK_RXD,
      Q => RSTATE(5));
  \RECBUFFER[0]_REG\: FD1P3AX port map (
      D => RECBUFFER(1),
      SP => UN8_RSTATE,
      CK => CLK_RXD,
      Q => RECBUFFER(0));
  \RECBUFFER[1]_REG\: FD1P3AX port map (
      D => RECBUFFER(2),
      SP => UN8_RSTATE,
      CK => CLK_RXD,
      Q => RECBUFFER(1));
  \RECBUFFER[2]_REG\: FD1P3AX port map (
      D => RECBUFFER(3),
      SP => UN8_RSTATE,
      CK => CLK_RXD,
      Q => RECBUFFER(2));
  \RECBUFFER[3]_REG\: FD1P3AX port map (
      D => RECBUFFER(4),
      SP => UN8_RSTATE,
      CK => CLK_RXD,
      Q => RECBUFFER(3));
  \RECBUFFER[4]_REG\: FD1P3AX port map (
      D => RECBUFFER(5),
      SP => UN8_RSTATE,
      CK => CLK_RXD,
      Q => RECBUFFER(4));
  \RECBUFFER[5]_REG\: FD1P3AX port map (
      D => RECBUFFER(6),
      SP => UN8_RSTATE,
      CK => CLK_RXD,
      Q => RECBUFFER(5));
  \RECBUFFER[6]_REG\: FD1P3AX port map (
      D => RECBUFFER(7),
      SP => UN8_RSTATE,
      CK => CLK_RXD,
      Q => RECBUFFER(6));
  \RECBUFFER[7]_REG\: FD1P3AX port map (
      D => RECBUFFER(8),
      SP => UN8_RSTATE,
      CK => CLK_RXD,
      Q => RECBUFFER(7));
  \RECBUFFER[8]_REG\: FD1P3AX port map (
      D => Uart_In_c,
      SP => UN8_RSTATE,
      CK => CLK_RXD,
      Q => RECBUFFER(8));
  START_REG: FD1S3DX 
  generic map(
    GSR => "DISABLED"
  )
  port map (
    D => VCC,
    CK => Uart_In_c_i,
    CD => GETDATAPC_I,
    Q => START);
  GETDATA_REG: FD1P3AY port map (
      D => START_I,
      SP => N_23_I,
      CK => CLK_RXD,
      Q => GETDATA_I);
  \DATAREC[0]_REG\: FD1P3AX port map (
      D => RECBUFFER(0),
      SP => UN13_RSTATE,
      CK => CLK_RXD,
      Q => GetComm(0));
  \DATAREC[1]_REG\: FD1P3AX port map (
      D => RECBUFFER(1),
      SP => UN13_RSTATE,
      CK => CLK_RXD,
      Q => GetComm(1));
  \DATAREC[2]_REG\: FD1P3AX port map (
      D => RECBUFFER(2),
      SP => UN13_RSTATE,
      CK => CLK_RXD,
      Q => GetComm(2));
  \DATAREC[3]_REG\: FD1P3AX port map (
      D => RECBUFFER(3),
      SP => UN13_RSTATE,
      CK => CLK_RXD,
      Q => GetComm(3));
  \DATAREC[4]_REG\: FD1P3AX port map (
      D => RECBUFFER(4),
      SP => UN13_RSTATE,
      CK => CLK_RXD,
      Q => GetComm(4));
  \DATAREC[5]_REG\: FD1P3AX port map (
      D => RECBUFFER(5),
      SP => UN13_RSTATE,
      CK => CLK_RXD,
      Q => GetComm(5));
  \DATAREC[6]_REG\: FD1P3AX port map (
      D => RECBUFFER(6),
      SP => UN13_RSTATE,
      CK => CLK_RXD,
      Q => GetComm(6));
  \DATAREC[7]_REG\: FD1P3AX port map (
      D => RECBUFFER(7),
      SP => UN13_RSTATE,
      CK => CLK_RXD,
      Q => GetComm(7));
  \DATAREC[8]_REG\: FD1P3AX port map (
      D => RECBUFFER(8),
      SP => UN13_RSTATE,
      CK => CLK_RXD,
      Q => GetComm(8));
  UN23_RSTATE_P4 <= not RSTATE_3(3) and RSTATE_3(0) and RSTATE_3(1) and RSTATE_3(2);
  RSTATE_3(0) <= not START and RSTATE(0);
  RSTATE_3(1) <= not START and RSTATE(1);
  RSTATE_3(2) <= not START and RSTATE(2);
  RSTATE_3(5) <= not START and RSTATE(5);
  RSTATE_3(3) <= not START and not RSTATE(3);
  UN23_RSTATE_AXBXC4 <= (START and not UN23_RSTATE_P4) or 
	  (RSTATE(4) and not UN23_RSTATE_P4) or 
	  (not START and not RSTATE(4) and UN23_RSTATE_P4);
  UN18_RSTATE_1 <= RSTATE(0) and RSTATE(1) and RSTATE(4) and RSTATE(5);
  UN1_RSTATE_2_1 <= not RSTATE(1) and not RSTATE(2) and not RSTATE(4);
  UN13_RSTATE_0 <= not RSTATE(0) and RSTATE(4) and RSTATE(5);
  UN13_RSTATE <= RSTATE(2) and RSTATE(3) and RSTATE_3(1) and UN13_RSTATE_0;
  RSTATE_5(0) <= (not RSTATE_3(0) and not UN1_RSTATE_2_1) or 
	  (not RSTATE_3(3) and not RSTATE_3(0)) or 
	  (RSTATE_3(3) and RSTATE_3(0) and not RSTATE_3(5) and UN1_RSTATE_2_1) or 
	  (not RSTATE_3(0) and RSTATE_3(5));
  UN23_RSTATE_AXBXC3 <= (not RSTATE_3(3) and not RSTATE_3(2)) or 
	  (not RSTATE_3(3) and not RSTATE_3(1)) or 
	  (not RSTATE_3(3) and not RSTATE_3(0)) or 
	  (RSTATE_3(3) and RSTATE_3(0) and RSTATE_3(1) and RSTATE_3(2));
  N_23_I <= (START) or 
	  (RSTATE(2) and RSTATE(3) and UN18_RSTATE_1);
  GETDATAPC_INT_7 <= GETDATA_I;
  NN_1 <= '0';
  NN_2 <= '1';
  GetDataPC <= GETDATAPC_INT_7;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library machxo;
use machxo.components.all;

entity BaudR is
port(
  GND :  in std_logic;
  CLK_TXD :  out std_logic;
  Clock_c :  in std_logic;
  Reset_c :  in std_logic;
  CLK_RXD :  out std_logic);
end BaudR;

architecture beh of BaudR is
  signal COUNT : std_logic_vector(5 downto 0);
  signal COUNT_I : std_logic_vector(1 downto 0);
  signal COUNT_QN_0 : std_logic_vector(2 downto 0);
  signal COUNT_3 : std_logic_vector(5 downto 0);
  signal COUNT_0 : std_logic_vector(0 to 0);
  signal COUNT_QN_1 : std_logic_vector(1 downto 0);
  signal COUNT_QN : std_logic_vector(5 downto 3);
  signal CLK_RXD_I : std_logic ;
  signal CLK_RXD_INT_6 : std_logic ;
  signal SUM1 : std_logic ;
  signal UN8_COUNT_AXBXC2 : std_logic ;
  signal UN8_COUNT_AXBXC3 : std_logic ;
  signal UN8_COUNT_AXBXC4 : std_logic ;
  signal UN4_COUNT : std_logic ;
  signal CLK_RXD_I_0 : std_logic ;
  signal CLK_RXD_QN : std_logic ;
  signal UN8_COUNT_P4 : std_logic ;
  signal UN4_COUNT_1 : std_logic ;
  signal CLK_TXD_INT_5 : std_logic ;
  signal NN_1 : std_logic ;
  signal VCC : std_logic ;
begin
  \GET_CLK_TXD.COUNT_I[0]\: INV port map (
      A => COUNT(0),
      Z => COUNT_I(0));
  CLK_RXD_I_Z47: INV port map (
      A => CLK_RXD_INT_6,
      Z => CLK_RXD_I);
  \GET_CLK_TXD.COUNT[0]_REG\: FD1S3AX port map (
      D => COUNT_I(0),
      CK => CLK_RXD_INT_6,
      Q => COUNT(0));
  \GET_CLK_TXD.COUNT[1]_REG\: FD1S3AX port map (
      D => SUM1,
      CK => CLK_RXD_INT_6,
      Q => COUNT_I(1));
  \GET_CLK_RXD.COUNT[0]_REG\: FD1S3AX port map (
      D => COUNT_3(0),
      CK => Clock_c,
      Q => COUNT_0(0));
  \GET_CLK_RXD.COUNT[1]_REG\: FD1S3AX port map (
      D => COUNT_3(1),
      CK => Clock_c,
      Q => COUNT(1));
  \GET_CLK_RXD.COUNT[2]_REG\: FD1S3AX port map (
      D => UN8_COUNT_AXBXC2,
      CK => Clock_c,
      Q => COUNT(2));
  \GET_CLK_RXD.COUNT[3]_REG\: FD1S3AX port map (
      D => UN8_COUNT_AXBXC3,
      CK => Clock_c,
      Q => COUNT(3));
  \GET_CLK_RXD.COUNT[4]_REG\: FD1S3AX port map (
      D => UN8_COUNT_AXBXC4,
      CK => Clock_c,
      Q => COUNT(4));
  \GET_CLK_RXD.COUNT[5]_REG\: FD1S3AX port map (
      D => COUNT_3(5),
      CK => Clock_c,
      Q => COUNT(5));
  CLK_RXD_REG: FD1P3AX port map (
      D => CLK_RXD_I,
      SP => UN4_COUNT,
      CK => Clock_c,
      Q => CLK_RXD_I_0);
  UN8_COUNT_P4 <= COUNT_0(0) and COUNT(1) and COUNT(2) and COUNT(3);
  SUM1 <= (CLK_TXD_INT_5 and not COUNT(0)) or 
	  (not CLK_TXD_INT_5 and COUNT(0));
  UN8_COUNT_AXBXC4 <= (COUNT(4) and not UN8_COUNT_P4) or 
	  (not COUNT(4) and UN8_COUNT_P4);
  UN4_COUNT_1 <= not COUNT(2) and not COUNT(4);
  UN8_COUNT_AXBXC2 <= (COUNT_0(0) and COUNT(1) and not COUNT(2)) or 
	  (not COUNT(1) and COUNT(2)) or 
	  (not COUNT_0(0) and COUNT(2));
  UN8_COUNT_AXBXC3 <= (COUNT_0(0) and COUNT(1) and COUNT(2) and not COUNT(3)) or 
	  (not COUNT(2) and COUNT(3)) or 
	  (not COUNT(1) and COUNT(3)) or 
	  (not COUNT_0(0) and COUNT(3));
  UN4_COUNT <= COUNT(1) and not COUNT(3) and COUNT(5) and UN4_COUNT_1;
  COUNT_3(5) <= (COUNT(5) and not UN4_COUNT and not UN8_COUNT_P4) or 
	  (COUNT(4) and not COUNT(5) and not UN4_COUNT and UN8_COUNT_P4) or 
	  (not COUNT(4) and COUNT(5) and not UN4_COUNT);
  COUNT_3(0) <= not COUNT_0(0) and not UN4_COUNT;
  COUNT_3(1) <= (COUNT_0(0) and not COUNT(1) and not UN4_COUNT) or 
	  (not COUNT_0(0) and COUNT(1) and not UN4_COUNT);
  CLK_RXD_INT_6 <= CLK_RXD_I_0;
  CLK_TXD_INT_5 <= COUNT_I(1);
  NN_1 <= '0';
  VCC <= '1';
  CLK_TXD <= CLK_TXD_INT_5;
  CLK_RXD <= CLK_RXD_INT_6;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library machxo;
use machxo.components.all;

entity UartSend is
port(
  PCM_Data : in std_logic_vector(7 downto 0);
  DioSel :  in std_logic;
  GND :  in std_logic;
  WrClock :  in std_logic;
  VCC :  in std_logic;
  Uart_Out_c :  out std_logic;