getpcm.vhm

PCM数据采集

--
-- Written by Synplicity
-- Product Version "Version 8.8L2"
-- Program "Synplify", Mapper "8.8.0, Build 018R"
-- Fri Jun 20 12:38:52 2008
--

--
-- Written by Synplify version 8.8.0, Build 018R
-- Fri Jun 20 12:38:52 2008
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library machxo;
use machxo.components.all;

entity PCM is
port(
  PCM_Data : out std_logic_vector(7 downto 0);
  Slot : in std_logic_vector(7 downto 0);
  WrClock :  out std_logic;
  VCC :  in std_logic;
  Reset_c :  in std_logic;
  PCM_CLK_c_i :  in std_logic;
  S_Data :  in std_logic;
  GND :  in std_logic;
  PCM_Fsync_c :  in std_logic);
end PCM;

architecture beh of PCM is
  signal DATA_TMP : std_logic_vector(3 downto 0);
  signal DATA_TMP_I : std_logic_vector(3 to 3);
  signal DATABUF : std_logic_vector(7 downto 0);
  signal DATABUF_2 : std_logic_vector(7 downto 0);
  signal COUNT : std_logic_vector(2 downto 0);
  signal COUNT_3 : std_logic_vector(2 downto 0);
  signal CHUNNEL_3 : std_logic_vector(7 downto 0);
  signal DATABUF_QN : std_logic_vector(7 downto 0);
  signal COUNT_QN : std_logic_vector(2 downto 0);
  signal CHUNNEL : std_logic_vector(7 downto 0);
  signal CHUNNEL_QN : std_logic_vector(7 downto 0);
  signal PCM_DATA_QN : std_logic_vector(7 downto 0);
  signal UN16_CHUNNEL_A_4 : std_logic_vector(7 downto 1);
  signal UN12_CHUNNEL : std_logic ;
  signal LASTFSYNC : std_logic ;
  signal L_DATA_1_SQMUXA_I : std_logic ;
  signal UN1_CHUNNEL_CRY_0_0_S0 : std_logic ;
  signal N_32 : std_logic ;
  signal UN1_CHUNNEL_CRY_6_0_S1 : std_logic ;
  signal UN1_CHUNNEL_CRY_6_0_S0 : std_logic ;
  signal UN1_CHUNNEL_CRY_4_0_S1 : std_logic ;
  signal UN1_CHUNNEL_CRY_4_0_S0 : std_logic ;
  signal UN1_CHUNNEL_CRY_2_0_S1 : std_logic ;
  signal UN1_CHUNNEL_CRY_2_0_S0 : std_logic ;
  signal UN1_CHUNNEL_CRY_0_0_S1 : std_logic ;
  signal UN2_FSYNC_I : std_logic ;
  signal LASTFSYNC_QN : std_logic ;
  signal L_DATA_I : std_logic ;
  signal L_DATA_QN : std_logic ;
  signal UN2_FSYNC : std_logic ;
  signal UN2_COUNT : std_logic ;
  signal I_19_0_S0 : std_logic ;
  signal I_19_0_S1 : std_logic ;
  signal N_28 : std_logic ;
  signal I_1_0_S1 : std_logic ;
  signal UN1_CHUNNEL_CRY_5 : std_logic ;
  signal UN1_CHUNNEL_CRY_6 : std_logic ;
  signal UN1_CHUNNEL_CRY_6_0_COUT1 : std_logic ;
  signal UN1_CHUNNEL_CRY_3 : std_logic ;
  signal UN1_CHUNNEL_CRY_4 : std_logic ;
  signal UN1_CHUNNEL_CRY_1 : std_logic ;
  signal UN1_CHUNNEL_CRY_2 : std_logic ;
  signal UN1_CHUNNEL_CRY_0 : std_logic ;
  signal UN16_CHUNNEL_A_4_CRY_5 : std_logic ;
  signal UN16_CHUNNEL_A_4_CRY_6 : std_logic ;
  signal UN16_CHUNNEL_A_4_CRY_6_0_COUT1 : std_logic ;
  signal UN16_CHUNNEL_A_4_CRY_3 : std_logic ;
  signal UN16_CHUNNEL_A_4_CRY_4 : std_logic ;
  signal UN16_CHUNNEL_A_4_CRY_1 : std_logic ;
  signal UN16_CHUNNEL_A_4_CRY_2 : std_logic ;
  signal UN16_CHUNNEL_A_4_CRY_0 : std_logic ;
  signal UN16_CHUNNEL_A_4_CRY_0_0_S0 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  \UN16_CHUNNEL_0.DATA_TMP_I[3]\: INV port map (
      A => DATA_TMP(3),
      Z => DATA_TMP_I(3));
  L_DATA_1_SQMUXA_I <= (UN12_CHUNNEL) or 
	  (not LASTFSYNC and PCM_Fsync_c);
  DATABUF_2(0) <= (S_Data and not PCM_Fsync_c) or 
	  (DATABUF(0) and not LASTFSYNC and PCM_Fsync_c) or 
	  (S_Data and LASTFSYNC);
  N_32 <= (not Slot(0) and not UN1_CHUNNEL_CRY_0_0_S0) or 
	  (Slot(0) and not PCM_Fsync_c and UN1_CHUNNEL_CRY_0_0_S0) or 
	  (not Slot(0) and PCM_Fsync_c and not LASTFSYNC) or 
	  (Slot(0) and LASTFSYNC and UN1_CHUNNEL_CRY_0_0_S0);
  DATABUF_2(1) <= (DATABUF(0) and not PCM_Fsync_c) or 
	  (DATABUF(1) and not LASTFSYNC and PCM_Fsync_c) or 
	  (DATABUF(0) and LASTFSYNC);
  DATABUF_2(2) <= (DATABUF(1) and not PCM_Fsync_c) or 
	  (DATABUF(2) and not LASTFSYNC and PCM_Fsync_c) or 
	  (DATABUF(1) and LASTFSYNC);
  DATABUF_2(3) <= (DATABUF(2) and not PCM_Fsync_c) or 
	  (DATABUF(3) and not LASTFSYNC and PCM_Fsync_c) or 
	  (DATABUF(2) and LASTFSYNC);
  DATABUF_2(4) <= (DATABUF(3) and not PCM_Fsync_c) or 
	  (DATABUF(4) and not LASTFSYNC and PCM_Fsync_c) or 
	  (DATABUF(3) and LASTFSYNC);
  DATABUF_2(5) <= (DATABUF(4) and not PCM_Fsync_c) or 
	  (DATABUF(5) and not LASTFSYNC and PCM_Fsync_c) or 
	  (DATABUF(4) and LASTFSYNC);
  DATABUF_2(6) <= (DATABUF(5) and not PCM_Fsync_c) or 
	  (DATABUF(6) and not LASTFSYNC and PCM_Fsync_c) or 
	  (DATABUF(5) and LASTFSYNC);
  DATABUF_2(7) <= (DATABUF(6) and not PCM_Fsync_c) or 
	  (DATABUF(7) and not LASTFSYNC and PCM_Fsync_c) or 
	  (DATABUF(6) and LASTFSYNC);
  COUNT_3(1) <= (COUNT(1) and not COUNT(0) and not PCM_Fsync_c) or 
	  (not COUNT(1) and COUNT(0) and not PCM_Fsync_c) or 
	  (COUNT(1) and not COUNT(0) and LASTFSYNC) or 
	  (not COUNT(1) and COUNT(0) and LASTFSYNC);
  COUNT_3(0) <= (not COUNT(0) and not PCM_Fsync_c) or 
	  (not COUNT(0) and LASTFSYNC);
  CHUNNEL_3(7) <= (UN1_CHUNNEL_CRY_6_0_S1 and not PCM_Fsync_c) or 
	  (UN1_CHUNNEL_CRY_6_0_S1 and LASTFSYNC);
  CHUNNEL_3(6) <= (UN1_CHUNNEL_CRY_6_0_S0 and not PCM_Fsync_c) or 
	  (UN1_CHUNNEL_CRY_6_0_S0 and LASTFSYNC);
  CHUNNEL_3(5) <= (UN1_CHUNNEL_CRY_4_0_S1 and not PCM_Fsync_c) or 
	  (UN1_CHUNNEL_CRY_4_0_S1 and LASTFSYNC);
  CHUNNEL_3(4) <= (UN1_CHUNNEL_CRY_4_0_S0 and not PCM_Fsync_c) or 
	  (UN1_CHUNNEL_CRY_4_0_S0 and LASTFSYNC);
  CHUNNEL_3(3) <= (UN1_CHUNNEL_CRY_2_0_S1 and not PCM_Fsync_c) or 
	  (UN1_CHUNNEL_CRY_2_0_S1 and LASTFSYNC);
  CHUNNEL_3(2) <= (UN1_CHUNNEL_CRY_2_0_S0 and not PCM_Fsync_c) or 
	  (UN1_CHUNNEL_CRY_2_0_S0 and LASTFSYNC);
  CHUNNEL_3(1) <= (UN1_CHUNNEL_CRY_0_0_S1 and not PCM_Fsync_c) or 
	  (UN1_CHUNNEL_CRY_0_0_S1 and LASTFSYNC);
  UN2_FSYNC_I <= (not PCM_Fsync_c) or 
	  (LASTFSYNC);
  LASTFSYNC_REG: FD1S3AX port map (
      D => PCM_Fsync_c,
      CK => PCM_CLK_c_i,
      Q => LASTFSYNC);
  \DATABUF[0]_REG\: FD1P3AX port map (
      D => S_Data,
      SP => UN2_FSYNC_I,
      CK => PCM_CLK_c_i,
      Q => DATABUF(0));
  \DATABUF[1]_REG\: FD1P3AX port map (
      D => DATABUF(0),
      SP => UN2_FSYNC_I,
      CK => PCM_CLK_c_i,
      Q => DATABUF(1));
  \DATABUF[2]_REG\: FD1P3AX port map (
      D => DATABUF(1),
      SP => UN2_FSYNC_I,
      CK => PCM_CLK_c_i,
      Q => DATABUF(2));
  \DATABUF[3]_REG\: FD1P3AX port map (
      D => DATABUF(2),
      SP => UN2_FSYNC_I,
      CK => PCM_CLK_c_i,
      Q => DATABUF(3));
  \DATABUF[4]_REG\: FD1P3AX port map (
      D => DATABUF(3),
      SP => UN2_FSYNC_I,
      CK => PCM_CLK_c_i,
      Q => DATABUF(4));
  \DATABUF[5]_REG\: FD1P3AX port map (
      D => DATABUF(4),
      SP => UN2_FSYNC_I,
      CK => PCM_CLK_c_i,
      Q => DATABUF(5));
  \DATABUF[6]_REG\: FD1P3AX port map (
      D => DATABUF(5),
      SP => UN2_FSYNC_I,
      CK => PCM_CLK_c_i,
      Q => DATABUF(6));
  \DATABUF[7]_REG\: FD1P3AX port map (
      D => DATABUF(6),
      SP => UN2_FSYNC_I,
      CK => PCM_CLK_c_i,
      Q => DATABUF(7));
  \COUNT[0]_REG\: FD1S3AX port map (
      D => COUNT_3(0),
      CK => PCM_CLK_c_i,
      Q => COUNT(0));
  \COUNT[1]_REG\: FD1S3AX port map (
      D => COUNT_3(1),
      CK => PCM_CLK_c_i,
      Q => COUNT(1));
  \COUNT[2]_REG\: FD1S3AX port map (
      D => COUNT_3(2),
      CK => PCM_CLK_c_i,
      Q => COUNT(2));
  \CHUNNEL[0]_REG\: FD1S3AX port map (
      D => CHUNNEL_3(0),
      CK => PCM_CLK_c_i,
      Q => CHUNNEL(0));
  \CHUNNEL[1]_REG\: FD1S3AX port map (
      D => CHUNNEL_3(1),
      CK => PCM_CLK_c_i,
      Q => CHUNNEL(1));
  \CHUNNEL[2]_REG\: FD1S3AX port map (
      D => CHUNNEL_3(2),
      CK => PCM_CLK_c_i,
      Q => CHUNNEL(2));
  \CHUNNEL[3]_REG\: FD1S3AX port map (
      D => CHUNNEL_3(3),
      CK => PCM_CLK_c_i,
      Q => CHUNNEL(3));
  \CHUNNEL[4]_REG\: FD1S3AX port map (
      D => CHUNNEL_3(4),
      CK => PCM_CLK_c_i,
      Q => CHUNNEL(4));
  \CHUNNEL[5]_REG\: FD1S3AX port map (
      D => CHUNNEL_3(5),
      CK => PCM_CLK_c_i,
      Q => CHUNNEL(5));
  \CHUNNEL[6]_REG\: FD1S3AX port map (
      D => CHUNNEL_3(6),
      CK => PCM_CLK_c_i,
      Q => CHUNNEL(6));
  \CHUNNEL[7]_REG\: FD1S3AX port map (
      D => CHUNNEL_3(7),
      CK => PCM_CLK_c_i,
      Q => CHUNNEL(7));
  \PCM_DATA[0]_REG\: FD1P3AX port map (
      D => DATABUF_2(0),
      SP => UN12_CHUNNEL,
      CK => PCM_CLK_c_i,
      Q => PCM_Data(0));
  \PCM_DATA[1]_REG\: FD1P3AX port map (
      D => DATABUF_2(1),
      SP => UN12_CHUNNEL,
      CK => PCM_CLK_c_i,
      Q => PCM_Data(1));
  \PCM_DATA[2]_REG\: FD1P3AX port map (
      D => DATABUF_2(2),
      SP => UN12_CHUNNEL,
      CK => PCM_CLK_c_i,
      Q => PCM_Data(2));
  \PCM_DATA[3]_REG\: FD1P3AX port map (
      D => DATABUF_2(3),
      SP => UN12_CHUNNEL,
      CK => PCM_CLK_c_i,
      Q => PCM_Data(3));
  \PCM_DATA[4]_REG\: FD1P3AX port map (
      D => DATABUF_2(4),
      SP => UN12_CHUNNEL,
      CK => PCM_CLK_c_i,
      Q => PCM_Data(4));
  \PCM_DATA[5]_REG\: FD1P3AX port map (
      D => DATABUF_2(5),
      SP => UN12_CHUNNEL,
      CK => PCM_CLK_c_i,
      Q => PCM_Data(5));
  \PCM_DATA[6]_REG\: FD1P3AX port map (
      D => DATABUF_2(6),
      SP => UN12_CHUNNEL,
      CK => PCM_CLK_c_i,
      Q => PCM_Data(6));
  \PCM_DATA[7]_REG\: FD1P3AX port map (
      D => DATABUF_2(7),
      SP => UN12_CHUNNEL,
      CK => PCM_CLK_c_i,
      Q => PCM_Data(7));
  L_DATA_REG: FD1P3AX port map (
      D => DATA_TMP_I(3),
      SP => L_DATA_1_SQMUXA_I,
      CK => PCM_CLK_c_i,
      Q => L_DATA_I);
  UN2_FSYNC <= PCM_Fsync_c and not LASTFSYNC;
  UN2_COUNT <= COUNT(0) and COUNT(1) and COUNT(2);
  COUNT_3(2) <= (COUNT(0) and COUNT(1) and not COUNT(2) and not UN2_FSYNC) or 
	  (not COUNT(1) and COUNT(2) and not UN2_FSYNC) or 
	  (not COUNT(0) and COUNT(2) and not UN2_FSYNC);
  UN12_CHUNNEL <= not COUNT_3(0) and not COUNT_3(1) and not COUNT_3(2) and not DATA_TMP(3);
  CHUNNEL_3(0) <= (UN1_CHUNNEL_CRY_0_0_S0 and not PCM_Fsync_c) or 
	  (UN1_CHUNNEL_CRY_0_0_S0 and LASTFSYNC);
  \UN16_CHUNNEL_0.I_19_0\: CCU2 
  generic map(
    INIT0 => "0x8421",
    INIT1 => "0x8421",
    INJECT1_0 => "YES",
    INJECT1_1 => "YES"
  )
  port map (
    A0 => CHUNNEL_3(4),
    B0 => CHUNNEL_3(5),
    C0 => UN16_CHUNNEL_A_4(4),
    D0 => UN16_CHUNNEL_A_4(5),
    A1 => CHUNNEL_3(6),
    B1 => CHUNNEL_3(7),
    C1 => UN16_CHUNNEL_A_4(6),
    D1 => UN16_CHUNNEL_A_4(7),
    CIN => DATA_TMP(1),
    COUT0 => DATA_TMP(2),
    COUT1 => DATA_TMP(3),
    S0 => I_19_0_S0,
    S1 => I_19_0_S1);
  \UN16_CHUNNEL_0.I_1_0\: CCU2 
  generic map(
    INIT0 => "0x0321",
    INIT1 => "0x8421",
    INJECT1_0 => "YES",
    INJECT1_1 => "YES"
  )
  port map (
    A0 => UN1_CHUNNEL_CRY_0_0_S1,
    B0 => N_32,
    C0 => UN16_CHUNNEL_A_4(1),
    D0 => UN2_FSYNC,
    A1 => CHUNNEL_3(2),
    B1 => CHUNNEL_3(3),
    C1 => UN16_CHUNNEL_A_4(2),
    D1 => UN16_CHUNNEL_A_4(3),
    CIN => GND,
    COUT0 => DATA_TMP(0),
    COUT1 => DATA_TMP(1),
    S0 => N_28,
    S1 => I_1_0_S1);
  UN1_CHUNNEL_CRY_6_0: CCU2 
  generic map(
    INIT0 => "0x300a",
    INIT1 => "0x300a",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => CHUNNEL(6),
    B0 => GND,
    C0 => GND,
    D0 => GND,
    A1 => CHUNNEL(7),
    B1 => GND,
    C1 => GND,
    D1 => GND,
    CIN => UN1_CHUNNEL_CRY_5,
    COUT0 => UN1_CHUNNEL_CRY_6,
    COUT1 => UN1_CHUNNEL_CRY_6_0_COUT1,
    S0 => UN1_CHUNNEL_CRY_6_0_S0,
    S1 => UN1_CHUNNEL_CRY_6_0_S1);
  UN1_CHUNNEL_CRY_4_0: CCU2 
  generic map(
    INIT0 => "0x300a",
    INIT1 => "0x300a",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => CHUNNEL(4),
    B0 => GND,
    C0 => GND,
    D0 => GND,
    A1 => CHUNNEL(5),
    B1 => GND,
    C1 => GND,
    D1 => GND,
    CIN => UN1_CHUNNEL_CRY_3,
    COUT0 => UN1_CHUNNEL_CRY_4,
    COUT1 => UN1_CHUNNEL_CRY_5,
    S0 => UN1_CHUNNEL_CRY_4_0_S0,
    S1 => UN1_CHUNNEL_CRY_4_0_S1);
  UN1_CHUNNEL_CRY_2_0: CCU2 
  generic map(
    INIT0 => "0x300a",
    INIT1 => "0x300a",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => CHUNNEL(2),
    B0 => GND,
    C0 => GND,
    D0 => GND,
    A1 => CHUNNEL(3),
    B1 => GND,
    C1 => GND,
    D1 => GND,
    CIN => UN1_CHUNNEL_CRY_1,
    COUT0 => UN1_CHUNNEL_CRY_2,
    COUT1 => UN1_CHUNNEL_CRY_3,
    S0 => UN1_CHUNNEL_CRY_2_0_S0,
    S1 => UN1_CHUNNEL_CRY_2_0_S1);
  UN1_CHUNNEL_CRY_0_0: CCU2 
  generic map(
    INIT0 => "0x300a",
    INIT1 => "0x300a",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => CHUNNEL(0),
    B0 => GND,
    C0 => GND,
    D0 => GND,
    A1 => CHUNNEL(1),
    B1 => GND,
    C1 => GND,
    D1 => GND,
    CIN => UN2_COUNT,
    COUT0 => UN1_CHUNNEL_CRY_0,
    COUT1 => UN1_CHUNNEL_CRY_1,
    S0 => UN1_CHUNNEL_CRY_0_0_S0,
    S1 => UN1_CHUNNEL_CRY_0_0_S1);
  UN16_CHUNNEL_A_4_CRY_6_0: CCU2 
  generic map(
    INIT0 => "0x300a",
    INIT1 => "0x300a",
    INJECT1_0 => "NO",
    INJECT1_1 => "NO"
  )
  port map (
    A0 => Slot(6),
    B0 => GND,
    C0 => GND,
    D0 => GND,
    A1 => Slot(7),
    B1 => GND,
    C1 => GND,
    D1 => GND,