fifo_dc.vht

PCM数据采集

-- VHDL instantiation for module FIFO_DC
-- 06/18/08  17:17:42
--

	COMPONENT FIFO_DC
	PORT(
		Data : IN std_logic_vector(8 downto 0);
		WrClock : IN std_logic;
		RdClock : IN std_logic;
		WrEn : IN std_logic;
		RdEn : IN std_logic;
		Reset : IN std_logic;
		RPReset : IN std_logic;          
		Q : OUT std_logic_vector(8 downto 0);
		Empty : OUT std_logic;
		Full : OUT std_logic
		);
	END COMPONENT;

BEGIN

-- change the 'instance_name' as you like.
	instance_name: FIFO_DC PORT MAP(
		Data => Data,
		WrClock => WrClock,
		RdClock => RdClock,
		WrEn => WrEn,
		RdEn => RdEn,
		Reset => Reset,
		RPReset => RPReset,
		Q => Q,
		Empty => Empty,
		Full => Full
	);



END;