uartsend.log

PCM数据采集

#Build: Synplify for Lattice 8.8L2, Build 008R, Dec  7 2006
#install: D:\ISPTOOLS7_0\SYNPBASE
#OS: Windows XP 5.1
#Hostname: STAR-PANCAT

#Implementation: GETPCM~1

#Thu Jun 19 21:20:42 2008

$ Start of Compile
#Thu Jun 19 21:20:42 2008

Synplicity VHDL Compiler, version 3.7.5, Build 159R, built Apr 13 2007
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved

@N: CD720 :"D:\ISPTOOLS7_0\SYNPBASE\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"D:\cpld\GETPCM~1\uartsend.vhd":6:7:6:14|Top entity is set to UartSend.
VHDL syntax check successful!
@N: CD630 :"D:\cpld\GETPCM~1\uartsend.vhd":6:7:6:14|Synthesizing work.uartsend.art_uartsend 
Post processing for work.uartsend.art_uartsend
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jun 19 21:20:43 2008

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Synplicity Generic Technology Mapper, Version 8.8.0, Build 018R, Built Apr 17 2007 19:29:01
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved
Product Version Version 8.8L2
@N: MF249 |Running in 32-bit mode.


RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)
@N:"d:\cpld\getpcm~1\uartsend.vhd":38:5:38:6|Found counter in view:work.UartSend(art_uartsend) inst tstate[3:0]

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Clock Buffers:
  Inserting Clock buffer for port SendClk,	TNM=SendClk
  Inserting Clock buffer for port Latch,	TNM=Latch


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 51MB)

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------

Net buffering Report for view:work.UartSend(art_uartsend):
No nets needed buffering.


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)
Found clock UartSend|SendClk with period 1000.00ns 
Found clock UartSend|Latch with period 1000.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Thu Jun 19 21:20:44 2008
#


Top view:               UartSend
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..


Performance Summary 
*******************


Worst slack in design: 995.339

                     Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock       Frequency     Frequency     Period        Period        Slack       Type         Group              
-------------------------------------------------------------------------------------------------------------------------
UartSend|SendClk     1.0 MHz       214.6 MHz     1000.000      4.661         995.339     inferred     Inferred_clkgroup_1
System               1.0 MHz       536.5 MHz     1000.000      1.864         998.136     system       default_clkgroup   
=========================================================================================================================





Clock Relationships
*******************

Clocks                              |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------------------------
Starting          Ending            |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------------------------
UartSend|Latch    UartSend|SendClk  |  Diff grp    -        |  No paths    -      |  No paths    -      |  No paths    -    
UartSend|SendClk  UartSend|SendClk  |  1000.000    995.339  |  No paths    -      |  No paths    -      |  No paths    -    
============================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port        Starting            User           Arrival     Required          
Name        Reference           Constraint     Time        Time         Slack
            Clock                                                            
-----------------------------------------------------------------------------
Data[0]     System (rising)     NA             0.000       997.492           
Data[1]     System (rising)     NA             0.000       997.492           
Data[2]     System (rising)     NA             0.000       997.492           
Data[3]     System (rising)     NA             0.000       997.492           
Data[4]     System (rising)     NA             0.000       997.492           
Data[5]     System (rising)     NA             0.000       997.492           
Data[6]     System (rising)     NA             0.000       997.492           
Data[7]     System (rising)     NA             0.000       997.492           
Data[8]     System (rising)     NA             0.000       997.492           
Latch       NA                  NA             NA          NA           NA   
Reset       System (rising)     NA             0.000       998.136           
SendClk     NA                  NA             NA          NA           NA   
=============================================================================


Output Ports: 

Port        Starting                      User           Arrival     Required          
Name        Reference                     Constraint     Time        Time         Slack
            Clock                                                                      
---------------------------------------------------------------------------------------
Busy        UartSend|SendClk (rising)     NA             4.661       1000.000          
UartOut     UartSend|SendClk (rising)     NA             4.619       1000.000          
=======================================================================================


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report
Part: lcmxo640c-5

Register bits: 16 of 640 (3%)
I/O cells:       14

Details:
FD1P3AX:        13
FD1P3AY:        1
FD1S3AY:        1
FD1S3DX:        1
GSR:            1
IB:             12
INV:            1
OB:             2
ORCALUT4:       19
VHI:            1
VLO:            1

Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)
Writing Analyst data base D:\cpld\GETPCM~1\UartSend.srm
@N: MF203 |Set autoconstraint_io 
Writing EDIF Netlist and constraint files
@N: MF203 |Set autoconstraint_io 
Version 8.8L2
Writing Verilog Simulation files
@N: MF203 |Set autoconstraint_io 
Writing VHDL Simulation files
@N: MF203 |Set autoconstraint_io 
@N: MF203 |Set autoconstraint_io 
Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Jun 19 21:20:45 2008

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