📄 getpcmdata_par.html
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<HEAD><TITLE>Place & Route Report</TITLE>
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<A name="Par"></A>PAR: Place And Route ispLever_v70_Prod_Build (55).
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation, All rights reserved.
Wed Jun 18 20:22:17 2008
D:/ispTOOLS7_0/ispfpga\bin\nt\par -f getpcmdata.p2t getpcmdata_map.ncd
getpcmdata.dir getpcmdata.prf
Preference file: getpcmdata.prf.
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
Level/ Number Timing Run NCD
Cost [ncd] Unrouted Score Time Status
---------- -------- -------- ----- ------------
5_1 * 0 0 40 Complete
* : Design saved.
par done!
Lattice Place and Route Report for Design "getpcmdata_map.ncd"
Wed Jun 18 20:22:17 2008
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
PAR: Place And Route ispLever_v70_Prod_Build (55).
Command line: D:/ispTOOLS7_0/ispfpga\bin\nt\par -f getpcmdata.p2t getpcmdata_map.ncd
getpcmdata.dir getpcmdata.prf
Preference file: getpcmdata.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
Loading design for application par from file getpcmdata_map.ncd.
Design name: GetPcm
NCD version: 3.2
Vendor: LATTICE
Device: LFXP2-17E
Package: PQFP208
Speed: 5
Loading device for application par from file 'mg5a50x47.nph' in
environment: D:/ispTOOLS7_0/ispfpga.
Package: Version 1.60, Status: FINAL
Speed Hardware Data: version 1.67.1.5
Ignore Preference Error(s): True
Dumping design to file F:/Temp/Tmp/neo_2.
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
PIO 8/364 2% used
8/146 5% bonded
IOLOGIC 1/364 <1% used
SLICE 164/8280 1% used
GSR 1/1 100% used
EBR 1/15 6% used
Number of Signals: 402
Number of Connections: 963
Pin Constraint Summary:
8 out of 8 pins locked (100% locked).
The following 4 signals are selected to use the primary clock routing resources:
Clock_c (driver: Clock, clk load #: 6)
RdClock_inferred_clock (driver: SLICE_42, clk load #: 28)
WrClock (driver: U5/SLICE_1, clk load #: 28)
CLK_RXD (driver: U3/SLICE_29, clk load #: 16)
WARNING - par: Signal "Clock_c" is selected to use Primary clock resources;
however its driver comp "Clock" is located at "52", which is not a
dedicated pin for connecting to Primary clock resources. General
routing has to be used to route this signal, and it may suffer
from excessive delay or skew.
No signal is selected as DCS clock.
The following 3 signals are selected to use the secondary clock routing resources:
GetDataPC (driver: u4/SLICE_37, clk load #: 5, sr load #: 1, ce load #: 0)
CLK_TXD (driver: U3/SLICE_30, clk load #: 9, sr load #: 0, ce load #: 0)
PCM_CLK_c (driver: PCM_CLK, clk load #: 17, sr load #: 0, ce load #: 0)
WARNING - par: Signal "PCM_CLK_c" is selected to use Secondary clock
resources; however its driver comp "PCM_CLK" is located at "197",
which is not a dedicated pin for connecting to Secondary clock
resources. General routing has to be used to route this signal,
and it may suffer from excessive delay or skew.
Signal Reset_c is selected as Global Set/Reset.
Starting Placer Phase 0.
..........
Finished Placer Phase 0. REAL time: 11 secs
Starting Placer Phase 1.
Placer score = 4129923.
.....................................
Placer score = 60904.
Finished Placer Phase 1. REAL time: 30 secs
Starting Placer Phase 2.
.
Placer score = 60019
Finished Placer Phase 2. REAL time: 30 secs
<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
Global Clock Resources:
CLK_PIN : 0 out of 8 (0%)
General PIO: 2 out of 364 (0%)
PLL : 0 out of 4 (0%)
DCS : 0 out of 8 (0%)
Quadrants All (TL, TR, BL, BR) - Global Clocks:
PRIMARY "Clock_c" from PIO "52", driver "Clock", clk load = 6
PRIMARY "RdClock_inferred_clock" from ROUTING "R22C2B.Q0", driver "SLICE_42", clk load = 28
PRIMARY "WrClock" from ROUTING "R22C46C.Q1", driver "U5/SLICE_1", clk load = 28
PRIMARY "CLK_RXD" from ROUTING "R28C46B.Q0", driver "U3/SLICE_29", clk load = 16
SECONDARY "GetDataPC" from ROUTING "R24C2B.Q0", driver "u4/SLICE_37", clk load = 5, ce load = 0, sr load = 1
SECONDARY "CLK_TXD" from ROUTING "R49C29A.Q0", driver "U3/SLICE_30", clk load = 9, ce load = 0, sr load = 0
SECONDARY "PCM_CLK_c" from PIO "197", driver "PCM_CLK", clk load = 17, ce load = 0, sr load = 0
PRIMARY : 4 out of 8 (50%)
DCS : 0 out of 2 (0%)
SECONDARY: 3 out of 4 (75%)
Edge Clocks:
FRC "CLK_TXD" from ROUTING "R49C29A.Q0", driver "U3/SLICE_30", bottom FRC0
I/O Usage Summary:
8 out of 364 (2%) PIO sites used.
8 out of 146 (5%) bonded PIO sites used.
Number of PIO comps: 8; differential: 0
Number of Vref pins used: 0
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The
use of the EBR block asynchronous reset requires that certain timing be met
between the clock and the reset within the memory block. See the device
specific datasheet for additional details.
DSP Utilization Summary:
-------------------------------------
DSP Block #: 1 2 3 4 5
# of MULT36X36B
# of MULT18X18B
# of MULT18X18MACB
# of MULT18X18ADDSUBB
# of MULT18X18ADDSUBSUMB
# of MULT9X9B
# of MULT9X9ADDSUBB
# of MULT9X9ADDSUBSUMB
Total placer CPU time: 30 secs
Dumping design to file getpcmdata.dir/5_1.ncd.
0 connections routed; 963 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net Clock_c is not placed on one
of the PIO sites which are dedicated for primary clocks. This
primary clock will be routed to a H-spine through general routing
resource or be routed as secondary clock and may suffer from
excessive delay or skew.
Completed router resource preassignment. Real time: 39 secs
Starting iterative routing.
For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.
End of iteration 1
963 successful; 0 unrouted; (0) real time: 40 secs
Dumping design to file getpcmdata.dir/5_1.ncd.
Total CPU time 39 secs
Total REAL time: 40 secs
Completely routed.
End of route. 963 routed (100.00%); 0 unrouted.
Checking DRC ...
No errors found.
Total REAL time to completion: 40 secs
All signals are completely routed.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation, All rights reserved.
Generated from the file 'D:\CPLD\FPGA\GetPcm\getpcmdata.par'
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