getpcmdata.mrp

PCM数据采集

               Lattice Mapping Report File for Design 'GetPcm'

Design Information
------------------

Command line:   D:\ispTOOLS7_0\ispfpga\bin\nt\map.exe -a MachXO -p LCMXO640C -t
     TQFP144 -s 5 getpcmdata.ngd -o getpcmdata_map.ncd -mp getpcmdata.mrp
     getpcmdata.lpf -c 0
Target Vendor:  LATTICE
Target Device:  LCMXO640CTQFP144
Target Speed:   5
Mapper:  mj5g00,  version:  ispLever_v70_Prod_Build (55)
Mapped on:  06/20/08  12:08:47

Design Summary
--------------

   Number of PFU registers:    89
   Number of SLICEs:            60 out of   320 (19%)
      SLICEs(logic/ROM):        60 out of   128 (47%)
      SLICEs(logic/ROM/RAM):     0 out of   192 (0%)
          As RAM:            0
          As Logic/ROM:      0
   Number of logic LUT4s:      80
   Number of distributed RAM:   0 (0 LUT4s)
   Number of ripple logic:     10 (20 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:     100
   Number of external PIOs: 17 out of 113 (15%)
   Number of 3-state buffers:   0
   Number of GSRs:  1 out of 1 (100%)
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   Number of TSALL: 0 out of 1 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  7
     Net GetDataPC: 5 loads, 5 rising, 0 falling (Driver: u4/GetData )
     Net WrClock: 1 loads, 1 rising, 0 falling (Driver: U5/L_Data )
     Net CLK_RXD: 16 loads, 16 rising, 0 falling (Driver: U3/CLK_RXD )
     Net Uart_In_c: 1 loads, 0 rising, 1 falling (Driver: PIO Uart_In )
     Net CLK_TXD: 9 loads, 9 rising, 0 falling (Driver: U3/Get_CLK_TXD_count_1 )
     Net Clock_c: 5 loads, 5 rising, 0 falling (Driver: PIO Clock )
     Net PCM_CLK_c: 15 loads, 0 rising, 15 falling (Driver: PIO PCM_CLK )
   Number of Clock Enables:  9
     Net U5/un12_chunnel: 4 loads, 4 LSLICEs
     Net U5/L_Data_1_sqmuxa_i: 1 loads, 1 LSLICEs
     Net U5/un2_fsync_i: 4 loads, 4 LSLICEs
     Net u4/un8_rstate: 5 loads, 5 LSLICEs
     Net u4/N_23_i: 1 loads, 1 LSLICEs
     Net u4/un13_rstate: 5 loads, 5 LSLICEs
     Net U3/un4_count: 1 loads, 1 LSLICEs
     Net u2/sendbuffer10_i: 1 loads, 1 LSLICEs
     Net u2/N_34_i: 7 loads, 7 LSLICEs
   Number of LSRs:  2

                                    Page 1




Design:  GetPcm                                        Date:  06/20/08  12:08:47

Design Summary (cont)
---------------------
     Net GetDataPC: 1 loads, 1 LSLICEs
     Net u2/N_36_i: 1 loads, 1 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net PCM_Fsync_c: 23 loads
     Net U5/lastfsync: 22 loads
     Net u2/Start: 18 loads
     Net u4/Start: 12 loads
     Net u2/N_34_i: 7 loads
     Net u2/tstate_1: 6 loads
     Net u4/rstate_0: 6 loads
     Net u4/rstate_1: 6 loads
     Net u4/rstate_2: 5 loads
     Net u4/rstate_4: 5 loads

IO (PIO) Attributes
-------------------

+---------------------+-----------+-----------+------------+------------+
| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
|                     |           |  IO_TYPE  | Register   |            |
+---------------------+-----------+-----------+------------+------------+
| Uart_Out            | OUTPUT    | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| Reset               | INPUT     | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| PCM_Dout            | INPUT     | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| PCM_Din             | INPUT     | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| PCM_Fsync           | INPUT     | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| PCM_CLK             | INPUT     | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| DioSel_LED          | OUTPUT    | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| Slot_LED_7          | OUTPUT    | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| Slot_LED_6          | OUTPUT    | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| Slot_LED_5          | OUTPUT    | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| Slot_LED_4          | OUTPUT    | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| Slot_LED_3          | OUTPUT    | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| Slot_LED_2          | OUTPUT    | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| Slot_LED_1          | OUTPUT    | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| Slot_LED_0          | OUTPUT    | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| Uart_In             | INPUT     | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+
| Clock               | INPUT     | LVCMOS33  |            |            |
+---------------------+-----------+-----------+------------+------------+

                                    Page 2




Design:  GetPcm                                        Date:  06/20/08  12:08:47


Removed logic
-------------

Signal Uart_In_c_i was merged into signal Uart_In_c
Signal PCM_CLK_c_i was merged into signal PCM_CLK_c
Signal u4/GetDataPC_i was merged into signal GetDataPC
Signal GND undriven or does not drive anything - clipped.
Signal VCC undriven or does not drive anything - clipped.
Signal U5/un16_chunnel_a_4_cry_2 undriven or does not drive anything - clipped.
Signal U5/un16_chunnel_a_4_cry_4 undriven or does not drive anything - clipped.
Signal U5/un16_chunnel_a_4_cry_6_0_COUT1 undriven or does not drive anything -
     clipped.
Signal U5/un16_chunnel_a_4_cry_6 undriven or does not drive anything - clipped.
Signal U5/un1_chunnel_cry_0 undriven or does not drive anything - clipped.
Signal U5/un1_chunnel_cry_2 undriven or does not drive anything - clipped.
Signal U5/un1_chunnel_cry_4 undriven or does not drive anything - clipped.
Signal U5/un1_chunnel_cry_6_0_COUT1 undriven or does not drive anything -
     clipped.
Signal U5/un1_chunnel_cry_6 undriven or does not drive anything - clipped.
Signal U5/I_1_0_S1 undriven or does not drive anything - clipped.
Signal U5/N_28 undriven or does not drive anything - clipped.
Signal U5/data_tmp_0 undriven or does not drive anything - clipped.
Signal U5/I_19_0_S1 undriven or does not drive anything - clipped.
Signal U5/I_19_0_S0 undriven or does not drive anything - clipped.
Signal U5/data_tmp_2 undriven or does not drive anything - clipped.
Signal U5/un16_chunnel_a_4_cry_0_0_S0 undriven or does not drive anything -
     clipped.
Signal U5/un16_chunnel_a_4_cry_0 undriven or does not drive anything - clipped.
Block Uart_In_c_i was optimized away.
Block PCM_CLK_c_i was optimized away.
Block u4/GetDataPC_i was optimized away.
Block GND_0 was optimized away.
Block VCC_0 was optimized away.

Symbol Cross Reference
----------------------

U5/SLICE_0 (PFU) covers blocks: U5/un16_chunnel_a_4_cry_0_0
SLICE_1 (PFU) covers blocks: Slot_1, Slot_2, U5/un16_chunnel_0_I_19_0
SLICE_2 (PFU) covers blocks: Slot_3, U5/un16_chunnel_0_I_1_0
U5/SLICE_3 (PFU) covers blocks: U5/un1_chunnel_cry_6_0
U5/SLICE_4 (PFU) covers blocks: U5/un1_chunnel_cry_4_0
U5/SLICE_5 (PFU) covers blocks: U5/un1_chunnel_cry_2_0
U5/SLICE_6 (PFU) covers blocks: U5/un1_chunnel_cry_0_0
U5/SLICE_7 (PFU) covers blocks: U5/un16_chunnel_a_4_cry_6_0
U5/SLICE_8 (PFU) covers blocks: U5/un16_chunnel_a_4_cry_4_0
U5/SLICE_9 (PFU) covers blocks: U5/un16_chunnel_a_4_cry_2_0
U3/SLICE_10 (PFU) covers blocks: U3/CLK_RXD_i, U3/CLK_RXD
U3/SLICE_11 (PFU) covers blocks: U3/un2_count_1_SUM1, U3/Get_CLK_TXD_count_1
u4/SLICE_17 (PFU) covers blocks: u4/DataRec_8
u4/SLICE_18 (PFU) covers blocks: u4/Start_i, u4/rstate_3_0, u4/GetData
U5/SLICE_19 (PFU) covers blocks: U5/databuf_2_0_0, U5/databuf_2_0_1,
     U5/PCM_Data_0, U5/PCM_Data_1
U5/SLICE_20 (PFU) covers blocks: U5/databuf_2_0_2, U5/databuf_2_0_3,
     U5/PCM_Data_2, U5/PCM_Data_3
U5/SLICE_21 (PFU) covers blocks: U5/databuf_2_0_4, U5/databuf_2_0_5,
     U5/PCM_Data_4, U5/PCM_Data_5

                                    Page 3




Design:  GetPcm                                        Date:  06/20/08  12:08:47

Symbol Cross Reference (cont)
-----------------------------
U5/SLICE_22 (PFU) covers blocks: U5/databuf_2_0_6, U5/databuf_2_0_7,
     U5/PCM_Data_6, U5/PCM_Data_7
U3/SLICE_27 (PFU) covers blocks: U3/Get_CLK_TXD_count_i_0,
     U3/Get_CLK_TXD_count_0
U3/SLICE_28 (PFU) covers blocks: U3/count_3_1, U3/un8_count_axbxc2,
     U3/Get_CLK_RXD_count_1, U3/Get_CLK_RXD_count_2
U3/SLICE_29 (PFU) covers blocks: U3/un8_count_axbxc3, U3/un8_count_axbxc4,
     U3/Get_CLK_RXD_count_3, U3/Get_CLK_RXD_count_4
U3/SLICE_30 (PFU) covers blocks: U3/count_3_5, U3/Get_CLK_RXD_un4_count,
     U3/Get_CLK_RXD_count_5
U3/SLICE_31 (PFU) covers blocks: U3/count_3_0, U3/un8_count_p4,
     U3/Get_CLK_RXD_count_0
U5/SLICE_32 (PFU) covers blocks: U5/chunnel_3_0, U5/chunnel_3_1, U5/chunnel_0,
     U5/chunnel_1
U5/SLICE_33 (PFU) covers blocks: U5/chunnel_3_2, U5/chunnel_3_3, U5/chunnel_2,
     U5/chunnel_3
U5/SLICE_34 (PFU) covers blocks: U5/chunnel_3_4, U5/chunnel_3_5, U5/chunnel_4,
     U5/chunnel_5
U5/SLICE_35 (PFU) covers blocks: U5/chunnel_3_6, U5/chunnel_3_7, U5/chunnel_6,
     U5/chunnel_7
U5/SLICE_36 (PFU) covers blocks: U5/count_3_0, U5/count_3_1, U5/count_0,
     U5/count_1
U5/SLICE_37 (PFU) covers blocks: U5/count_3_2, U5/un2_fsync, U5/count_2,
     U5/lastfsync
SLICE_38 (PFU) covers blocks: S_Data_0, U5/databuf_0, U5/databuf_1
u2/SLICE_43 (PFU) covers blocks: u2/UartOut_2_f0, u2/un1_tstate_1, u2/UartOut
U5/SLICE_44 (PFU) covers blocks: U5/un16_chunnel_0_data_tmp_i_3,
     U5/un12_chunnel, U5/L_Data
SLICE_45 (PFU) covers blocks: u2/N_34_i, u2/Start
u2/SLICE_46 (PFU) covers blocks: u2/Start_i, u2/N_36_i, u2/SendComp
u2/SLICE_47 (PFU) covers blocks: u2/sendbuffer_4_0_0, u2/sendbuffer_4_0_1,
     u2/sendbuffer_0, u2/sendbuffer_1
u2/SLICE_48 (PFU) covers blocks: u2/sendbuffer_4_0_2, u2/sendbuffer_4_0_3,
     u2/sendbuffer_2, u2/sendbuffer_3
u2/SLICE_49 (PFU) covers blocks: u2/sendbuffer_4_0_4, u2/sendbuffer_4_0_5,
     u2/sendbuffer_4, u2/sendbuffer_5
u2/SLICE_50 (PFU) covers blocks: u2/sendbuffer_4_0_6, u2/sendbuffer_4_0_7,
     u2/sendbuffer_6, u2/sendbuffer_7
u2/SLICE_51 (PFU) covers blocks: u2/N_30_i, u2/sendbuffer10_i, u2/sendbuffer_8
u2/SLICE_52 (PFU) covers blocks: u2/N_6_i, u2/tstate_n1, u2/tstate_0,
     u2/tstate_1
u2/SLICE_53 (PFU) covers blocks: u2/tstate_n2, u2/tstate_n3, u2/tstate_2,
     u2/tstate_3
SLICE_54 (PFU) covers blocks: u4/un8_rstate, u4/Start
u4/SLICE_56 (PFU) covers blocks: u4/recbuffer_2, u4/recbuffer_1
u4/SLICE_57 (PFU) covers blocks: u4/recbuffer_4, u4/recbuffer_3
SLICE_58 (PFU) covers blocks: U3/Get_CLK_RXD_un4_count_1, u2/tstate_5,
     u4/recbuffer_6, u4/recbuffer_7
SLICE_59 (PFU) covers blocks: U5/un16_chunnel_0_I_6, U5/un2_count,
     u4/recbuffer_8, u4/recbuffer_0
u4/SLICE_60 (PFU) covers blocks: u4/rstate_5_0, u4/un23_rstate_axbxc1,
     u4/rstate_3_0, u4/rstate_0, u4/rstate_1
u4/SLICE_61 (PFU) covers blocks: u4/un23_rstate_axbxc2, u4/rstate_3_1,
     u4/un23_rstate_axbxc3, u4/rstate_2, u4/rstate_3
u4/SLICE_62 (PFU) covers blocks: u4/un23_rstate_axbxc4, u4/un23_rstate_axbxc5,
     u4/rstate_4, u4/rstate_5

                                    Page 4




Design:  GetPcm                                        Date:  06/20/08  12:08:47

Symbol Cross Reference (cont)
-----------------------------
SLICE_63 (PFU) covers blocks: u4/un23_rstate_p4, u4/rstate_3_3, U5/databuf_6,
     U5/databuf_7
SLICE_64 (PFU) covers blocks: u4/rstate_3_1, u4/un13_rstate, Slot_4, Slot_5
SLICE_65 (PFU) covers blocks: u4/un18_rstate_1, u4/N_23_i, U5/databuf_4,
     U5/databuf_5
SLICE_66 (PFU) covers blocks: U5/L_Data_1_sqmuxa_i, U5/un2_fsync_i, DioSel,
     Slot_0
SLICE_67 (PFU) covers blocks: u4/rstate_3_2, u4/un1_rstate_2_1, Slot_6, Slot_7
SLICE_68 (PFU) covers blocks: u4/rstate_3_5, u4/un13_rstate_0, U5/databuf_2,
     U5/databuf_3
u4/SLICE_69 (PFU) covers blocks: u4/DataRec_1, u4/DataRec_0
u4/SLICE_70 (PFU) covers blocks: u4/DataRec_3, u4/DataRec_2
u4/SLICE_71 (PFU) covers blocks: u4/DataRec_5, u4/DataRec_4
u4/SLICE_72 (PFU) covers blocks: u4/DataRec_7, u4/DataRec_6
u4/SLICE_82 (PFU) covers blocks: u4/recbuffer_5
Uart_Out (PIC/PIO) covers blocks: Uart_Out_pad
Reset (PIC/PIO) covers blocks: Reset_pad
PCM_Dout (PIC/PIO) covers blocks: PCM_Dout_pad
PCM_Din (PIC/PIO) covers blocks: PCM_Din_pad
PCM_Fsync (PIC/PIO) covers blocks: PCM_Fsync_pad
PCM_CLK (PIC/PIO) covers blocks: PCM_CLK_pad
DioSel_LED (PIC/PIO) covers blocks: DioSel_LED_pad