baudr.log

PCM数据采集

#Build: Synplify for Lattice 9.0L1, Build 024R, Nov 13 2007
#install: D:\ISPTOOLS7_0\SYNPBASE
#OS: Windows XP 5.1
#Hostname: STAR-PANCAT

#Implementation: getpcm

#Wed Jun 18 10:49:03 2008

$ Start of Compile
#Wed Jun 18 10:49:03 2008

Synplicity VHDL Compiler, version 1.0, Build 157R, built Nov 13 2007
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved

@N: CD720 :"D:\ISPTOOLS7_0\SYNPBASE\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"D:\cpld\fpga\getpcm\baudr.vhd":5:7:5:11|Top entity is set to BaudR.
VHDL syntax check successful!
@N: CD630 :"D:\cpld\fpga\getpcm\baudr.vhd":5:7:5:11|Synthesizing work.baudr.art_baudr 
Post processing for work.baudr.art_baudr
@N: CL177 :"D:\cpld\fpga\getpcm\baudr.vhd":37:1:37:2|Sharing sequential element CLK_TXD.
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jun 18 10:49:03 2008

###########################################################]

Total runtime: 00h:00m:01s realtime
Synplicity Generic Technology Mapper, Version 9.0.0, Build 139R, Built Nov 13 2007 20:48:37
Copyright (C) 1994-2007, Synplicity Inc.  All Rights Reserved
Product Version Version 9.0L1
@N: MF249 |Running in 32-bit mode.


RTL optimization done.

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)
Automatic dissolve during optimization of view:work.BaudR(art_baudr) of un2_count_1(PM_ADDC__0_2_lfxp2_17e)

Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 51MB)

Clock Buffers:
  Inserting Clock buffer for port Clock,	TNM=Clock


Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 52MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)

Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 52MB)
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:00s		     0.77ns		  14 /         9
   2		0h:00m:00s		     0.77ns		  13 /         9
   3		0h:00m:00s		     0.77ns		  13 /         9
   4		0h:00m:00s		     0.77ns		  13 /         9
------------------------------------------------------------

Net buffering Report for view:work.BaudR(art_baudr):
No nets needed buffering.


Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 52MB)
Found clock BaudR|Clock with period 5.00ns 
Found clock BaudR|CLK_RXD_inferred_clock with period 5.00ns 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Jun 18 10:49:08 2008
#


Top view:               BaudR
Requested Frequency:    200.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..


Performance Summary 
*******************


Worst slack in design: 0.766

                                 Requested     Estimated     Requested     Estimated               Clock        Clock              
Starting Clock                   Frequency     Frequency     Period        Period        Slack     Type         Group              
-----------------------------------------------------------------------------------------------------------------------------------
BaudR|CLK_RXD_inferred_clock     200.0 MHz     236.2 MHz     5.000         4.234         0.766     inferred     Inferred_clkgroup_1
BaudR|Clock                      200.0 MHz     238.8 MHz     5.000         4.187         0.813     inferred     Inferred_clkgroup_0
System                           200.0 MHz     489.7 MHz     5.000         2.042         2.958     system       default_clkgroup   
===================================================================================================================================





Clock Relationships
*******************

Clocks                                                      |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------------------------------------
Starting                      Ending                        |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------------------------------------------------
BaudR|Clock                   BaudR|Clock                   |  5.000       0.813  |  No paths    -      |  No paths    -      |  No paths    -    
BaudR|CLK_RXD_inferred_clock  BaudR|CLK_RXD_inferred_clock  |  5.000       0.766  |  No paths    -      |  No paths    -      |  No paths    -    
==================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port      Starting            User           Arrival     Required          
Name      Reference           Constraint     Time        Time         Slack
          Clock                                                            
---------------------------------------------------------------------------
Clock     NA                  NA             NA          NA           NA   
Reset     System (rising)     NA             0.000       2.958             
===========================================================================


Output Ports: 

Port        Starting                                  User           Arrival     Required          
Name        Reference                                 Constraint     Time        Time         Slack
            Clock                                                                                  
---------------------------------------------------------------------------------------------------
CLK_RXD     NA                                        NA             NA          NA           NA   
CLK_TXD     BaudR|CLK_RXD_inferred_clock (rising)     NA             4.234       5.000             
===================================================================================================


##### END OF TIMING REPORT #####]

---------------------------------------
Resource Usage Report
Part: lfxp2_17e-5

Register bits: 9 of 16560 (0%)
I/O cells:       4

Details:
FD1P3AX:        1
FD1S3AX:        8
GSR:            1
IB:             2
INV:            2
OB:             2
ORCALUT4:       10
VHI:            1
VLO:            1

Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 52MB)
Writing Analyst data base D:\cpld\fpga\getpcm\BaudR.srm
@N: MF203 |Set autoconstraint_io 
Writing EDIF Netlist and constraint files
@N: MF203 |Set autoconstraint_io 
Version 9.0L1
Writing Verilog Simulation files
@N: MF203 |Set autoconstraint_io 
Writing VHDL Simulation files
@N: MF203 |Set autoconstraint_io 
@N: MF203 |Set autoconstraint_io 
Mapper successful!
Process took 0h:00m:05s realtime, 0h:00m:01s cputime
# Wed Jun 18 10:49:10 2008

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Total runtime: 00h:00m:07s realtime