fifo_dc_generate.log

PCM数据采集

Starting process: 

SCUBA, Version ispLever_v70_Prod_Build (55)
Wed Jun 18 17:17:15 2008

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation,  All rights reserved.

BEGIN SCUBA Module Synthesis

    Issued command   : D:\ispTOOLS7_0\ispfpga\bin\nt\scuba.exe -w -n FIFO_DC -lang vhdl -synth synplify -bus_exp 7 -bb -arch mg5a00 -type fifodc -addr_width 9 -data_width 9 -num_words 512 -no_enable -pe -1 -pf -1 -e 
    Circuit name     : FIFO_DC
    Module type      : ebfifo
    Module Version   : 4.3
    Ports            : 
	Inputs       : Data[8:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
	Outputs      : Q[8:0], Empty, Full
    I/O buffer       : not inserted
    EDIF output      : suppressed
    VHDL output      : FIFO_DC.vhd
    VHDL template    : FIFO_DC_tmpl.vhd
    VHDL testbench   : tb_FIFO_DC_tmpl.vhd
    VHDL purpose     : for synthesis and simulation
    Bus notation     : big endian
    Report output    : FIFO_DC.srp
    Estimated Resource Usage:
            LUT : 97
            EBR : 1
            Reg : 102

END   SCUBA Module Synthesis

File: FIFO_DC.lpc created.


End process: completed successfully.


Total Warnings:  0

Total Errors:  0