getpcm.vm

PCM数据采集

	.D(data_tmp_i[3]),
	.SP(L_Data_1_sqmuxa_i),
	.CK(PCM_CLK_c_i),
	.Q(L_Data)
);
assign un2_fsync = (PCM_Fsync_c & ~lastfsync);
assign un2_count = (count[0] & count[1] & count[2]);
assign count_3[2] = (count[0] & count[1] & ~count[2] & ~un2_fsync) | (~count[0] & 
   count[2] & ~un2_fsync) | (~count[1] & count[2] & ~un2_fsync) | (~count[0] & 
   count[1] & count[2] & ~un2_fsync);
assign un12_chunnel = (~count_3[0] & ~count_3[1] & ~count_3[2] & ~data_tmp[3]);
assign chunnel_3[0] = (un1_chunnel_cry_0_0_S0 & lastfsync) | (un1_chunnel_cry_0_0_S0 & 
   ~PCM_Fsync_c) | (un1_chunnel_cry_0_0_S0 & lastfsync & PCM_Fsync_c);
// @10:107
  CCU2 \un16_chunnel_0.I_19_0  (
	.A0(chunnel_3[4]),
	.B0(chunnel_3[5]),
	.C0(un16_chunnel_a_4[4]),
	.D0(un16_chunnel_a_4[5]),
	.A1(chunnel_3[6]),
	.B1(chunnel_3[7]),
	.C1(un16_chunnel_a_4[6]),
	.D1(un16_chunnel_a_4[7]),
	.CIN(data_tmp[1]),
	.COUT0(data_tmp[2]),
	.COUT1(data_tmp[3]),
	.S0(I_19_0_S0),
	.S1(I_19_0_S1)
);
defparam \un16_chunnel_0.I_19_0 .INIT0=16'h8421;
defparam \un16_chunnel_0.I_19_0 .INIT1=16'h8421;
defparam \un16_chunnel_0.I_19_0 .INJECT1_0="YES";
defparam \un16_chunnel_0.I_19_0 .INJECT1_1="YES";
// @10:107
  CCU2 \un16_chunnel_0.I_1_0  (
	.A0(un1_chunnel_cry_0_0_S1),
	.B0(N_32),
	.C0(un16_chunnel_a_4[1]),
	.D0(un2_fsync),
	.A1(chunnel_3[2]),
	.B1(chunnel_3[3]),
	.C1(un16_chunnel_a_4[2]),
	.D1(un16_chunnel_a_4[3]),
	.CIN(GND),
	.COUT0(data_tmp[0]),
	.COUT1(data_tmp[1]),
	.S0(N_28),
	.S1(I_1_0_S1)
);
defparam \un16_chunnel_0.I_1_0 .INIT0=16'h0321;
defparam \un16_chunnel_0.I_1_0 .INIT1=16'h8421;
defparam \un16_chunnel_0.I_1_0 .INJECT1_0="YES";
defparam \un16_chunnel_0.I_1_0 .INJECT1_1="YES";
// @4:77
  CCU2 un1_chunnel_cry_6_0 (
	.A0(chunnel[6]),
	.B0(GND),
	.C0(GND),
	.D0(GND),
	.A1(chunnel[7]),
	.B1(GND),
	.C1(GND),
	.D1(GND),
	.CIN(un1_chunnel_cry_5),
	.COUT0(un1_chunnel_cry_6),
	.COUT1(un1_chunnel_cry_6_0_COUT1),
	.S0(un1_chunnel_cry_6_0_S0),
	.S1(un1_chunnel_cry_6_0_S1)
);
defparam un1_chunnel_cry_6_0.INIT0=16'h300a;
defparam un1_chunnel_cry_6_0.INIT1=16'h300a;
defparam un1_chunnel_cry_6_0.INJECT1_0="NO";
defparam un1_chunnel_cry_6_0.INJECT1_1="NO";
// @4:77
  CCU2 un1_chunnel_cry_4_0 (
	.A0(chunnel[4]),
	.B0(GND),
	.C0(GND),
	.D0(GND),
	.A1(chunnel[5]),
	.B1(GND),
	.C1(GND),
	.D1(GND),
	.CIN(un1_chunnel_cry_3),
	.COUT0(un1_chunnel_cry_4),
	.COUT1(un1_chunnel_cry_5),
	.S0(un1_chunnel_cry_4_0_S0),
	.S1(un1_chunnel_cry_4_0_S1)
);
defparam un1_chunnel_cry_4_0.INIT0=16'h300a;
defparam un1_chunnel_cry_4_0.INIT1=16'h300a;
defparam un1_chunnel_cry_4_0.INJECT1_0="NO";
defparam un1_chunnel_cry_4_0.INJECT1_1="NO";
// @4:77
  CCU2 un1_chunnel_cry_2_0 (
	.A0(chunnel[2]),
	.B0(GND),
	.C0(GND),
	.D0(GND),
	.A1(chunnel[3]),
	.B1(GND),
	.C1(GND),
	.D1(GND),
	.CIN(un1_chunnel_cry_1),
	.COUT0(un1_chunnel_cry_2),
	.COUT1(un1_chunnel_cry_3),
	.S0(un1_chunnel_cry_2_0_S0),
	.S1(un1_chunnel_cry_2_0_S1)
);
defparam un1_chunnel_cry_2_0.INIT0=16'h300a;
defparam un1_chunnel_cry_2_0.INIT1=16'h300a;
defparam un1_chunnel_cry_2_0.INJECT1_0="NO";
defparam un1_chunnel_cry_2_0.INJECT1_1="NO";
// @4:77
  CCU2 un1_chunnel_cry_0_0 (
	.A0(chunnel[0]),
	.B0(GND),
	.C0(GND),
	.D0(GND),
	.A1(chunnel[1]),
	.B1(GND),
	.C1(GND),
	.D1(GND),
	.CIN(un2_count),
	.COUT0(un1_chunnel_cry_0),
	.COUT1(un1_chunnel_cry_1),
	.S0(un1_chunnel_cry_0_0_S0),
	.S1(un1_chunnel_cry_0_0_S1)
);
defparam un1_chunnel_cry_0_0.INIT0=16'h300a;
defparam un1_chunnel_cry_0_0.INIT1=16'h300a;
defparam un1_chunnel_cry_0_0.INJECT1_0="NO";
defparam un1_chunnel_cry_0_0.INJECT1_1="NO";
// @4:82
  CCU2 un16_chunnel_a_4_cry_6_0 (
	.A0(Slot[6]),
	.B0(GND),
	.C0(GND),
	.D0(GND),
	.A1(Slot[7]),
	.B1(GND),
	.C1(GND),
	.D1(GND),
	.CIN(un16_chunnel_a_4_cry_5),
	.COUT0(un16_chunnel_a_4_cry_6),
	.COUT1(un16_chunnel_a_4_cry_6_0_COUT1),
	.S0(un16_chunnel_a_4[6]),
	.S1(un16_chunnel_a_4[7])
);
defparam un16_chunnel_a_4_cry_6_0.INIT0=16'h300a;
defparam un16_chunnel_a_4_cry_6_0.INIT1=16'h300a;
defparam un16_chunnel_a_4_cry_6_0.INJECT1_0="NO";
defparam un16_chunnel_a_4_cry_6_0.INJECT1_1="NO";
// @4:82
  CCU2 un16_chunnel_a_4_cry_4_0 (
	.A0(Slot[4]),
	.B0(GND),
	.C0(GND),
	.D0(GND),
	.A1(Slot[5]),
	.B1(GND),
	.C1(GND),
	.D1(GND),
	.CIN(un16_chunnel_a_4_cry_3),
	.COUT0(un16_chunnel_a_4_cry_4),
	.COUT1(un16_chunnel_a_4_cry_5),
	.S0(un16_chunnel_a_4[4]),
	.S1(un16_chunnel_a_4[5])
);
defparam un16_chunnel_a_4_cry_4_0.INIT0=16'h300a;
defparam un16_chunnel_a_4_cry_4_0.INIT1=16'h300a;
defparam un16_chunnel_a_4_cry_4_0.INJECT1_0="NO";
defparam un16_chunnel_a_4_cry_4_0.INJECT1_1="NO";
// @4:82
  CCU2 un16_chunnel_a_4_cry_2_0 (
	.A0(Slot[2]),
	.B0(GND),
	.C0(GND),
	.D0(GND),
	.A1(Slot[3]),
	.B1(GND),
	.C1(GND),
	.D1(GND),
	.CIN(un16_chunnel_a_4_cry_1),
	.COUT0(un16_chunnel_a_4_cry_2),
	.COUT1(un16_chunnel_a_4_cry_3),
	.S0(un16_chunnel_a_4[2]),
	.S1(un16_chunnel_a_4[3])
);
defparam un16_chunnel_a_4_cry_2_0.INIT0=16'h300a;
defparam un16_chunnel_a_4_cry_2_0.INIT1=16'h300a;
defparam un16_chunnel_a_4_cry_2_0.INJECT1_0="NO";
defparam un16_chunnel_a_4_cry_2_0.INJECT1_1="NO";
// @4:82
  CCU2 un16_chunnel_a_4_cry_0_0 (
	.A0(Slot[0]),
	.B0(GND),
	.C0(GND),
	.D0(GND),
	.A1(Slot[1]),
	.B1(GND),
	.C1(GND),
	.D1(GND),
	.CIN(VCC),
	.COUT0(un16_chunnel_a_4_cry_0),
	.COUT1(un16_chunnel_a_4_cry_1),
	.S0(un16_chunnel_a_4_cry_0_0_S0),
	.S1(un16_chunnel_a_4[1])
);
defparam un16_chunnel_a_4_cry_0_0.INIT0=16'h300a;
defparam un16_chunnel_a_4_cry_0_0.INIT1=16'h300a;
defparam un16_chunnel_a_4_cry_0_0.INJECT1_0="NO";
defparam un16_chunnel_a_4_cry_0_0.INJECT1_1="NO";
//@10:107
  assign NN_1 = 1'b0;
  assign NN_2 = 1'b1;
assign WrClock = L_Data;
endmodule /* PCM */

module GetPcm (
  Reset,
  Clock,
  Uart_In,
  Uart_Out,
  Slot_LED,
  DioSel_LED,
  PCM_CLK,
  PCM_Fsync,
  PCM_Din,
  PCM_Dout
)
;
input Reset ;
input Clock ;
input Uart_In ;
output Uart_Out ;
output [7:0] Slot_LED ;
output DioSel_LED ;
input PCM_CLK ;
input PCM_Fsync ;
input PCM_Din ;
input PCM_Dout ;
wire Reset ;
wire Clock ;
wire Uart_In ;
wire Uart_Out ;
wire DioSel_LED ;
wire PCM_CLK ;
wire PCM_Fsync ;
wire PCM_Din ;
wire PCM_Dout ;
wire [7:0] PCM_Data;
wire [8:0] GetComm;
wire [7:0] Slot;
wire [7:0] Slot_QN;
wire CLK_TXD ;
wire WrClock ;
wire GetDataPC ;
wire S_Data ;
wire DioSel ;
wire CLK_RXD ;
wire GND ;
wire VCC ;
wire Reset_c ;
wire Clock_c ;
wire Uart_In_c ;
wire Uart_Out_c ;
wire PCM_CLK_c ;
wire PCM_Fsync_c ;
wire PCM_Din_c ;
wire PCM_Dout_c ;
wire DioSel_QN ;
wire PCM_CLK_c_i ;
wire Uart_In_c_i ;
wire GND_Z ;
wire VCC_Z ;
// @10:107
  PUR PUR_INST (
	.PUR(VCC)
);
  VLO GND_0 (
	.Z(GND)
);
  VHI VCC_0 (
	.Z(VCC)
);
// @4:61
  INV Uart_In_c_i_cZ (
	.A(Uart_In_c),
	.Z(Uart_In_c_i)
);
// @4:61
  INV PCM_CLK_c_i_cZ (
	.A(PCM_CLK_c),
	.Z(PCM_CLK_c_i)
);
// @10:129
  FD1S3AX \Slot_Z[0]  (
	.D(GetComm[0]),
	.CK(GetDataPC),
	.Q(Slot[0])
);
// @10:129
  FD1S3AX \Slot_Z[1]  (
	.D(GetComm[1]),
	.CK(GetDataPC),
	.Q(Slot[1])
);
// @10:129
  FD1S3AX \Slot_Z[2]  (
	.D(GetComm[2]),
	.CK(GetDataPC),
	.Q(Slot[2])
);
// @10:129
  FD1S3AX \Slot_Z[3]  (
	.D(GetComm[3]),
	.CK(GetDataPC),
	.Q(Slot[3])
);
// @10:129
  FD1S3AX \Slot_Z[4]  (
	.D(GetComm[4]),
	.CK(GetDataPC),
	.Q(Slot[4])
);
// @10:129
  FD1S3AX \Slot_Z[5]  (
	.D(GetComm[5]),
	.CK(GetDataPC),
	.Q(Slot[5])
);
// @10:129
  FD1S3AX \Slot_Z[6]  (
	.D(GetComm[6]),
	.CK(GetDataPC),
	.Q(Slot[6])
);
// @10:129
  FD1S3AX \Slot_Z[7]  (
	.D(GetComm[7]),
	.CK(GetDataPC),
	.Q(Slot[7])
);
// @10:129
  FD1S3AX DioSel_Z (
	.D(GetComm[8]),
	.CK(GetDataPC),
	.Q(DioSel)
);
  GSR GSR_INST (
	.GSR(Reset_c)
);
// @10:19
  IB PCM_Dout_pad (
	.I(PCM_Dout),
	.O(PCM_Dout_c)
);
// @10:18
  IB PCM_Din_pad (
	.I(PCM_Din),
	.O(PCM_Din_c)
);
// @10:17
  IB PCM_Fsync_pad (
	.I(PCM_Fsync),
	.O(PCM_Fsync_c)
);
// @10:16
  IB PCM_CLK_pad (
	.I(PCM_CLK),
	.O(PCM_CLK_c)
);
// @10:15
  OB DioSel_LED_pad (
	.I(DioSel),
	.O(DioSel_LED)
);
// @10:14
  OB \Slot_LED_pad[7]  (
	.I(Slot[7]),
	.O(Slot_LED[7])
);
// @10:14
  OB \Slot_LED_pad[6]  (
	.I(Slot[6]),
	.O(Slot_LED[6])
);
// @10:14
  OB \Slot_LED_pad[5]  (
	.I(Slot[5]),
	.O(Slot_LED[5])
);
// @10:14
  OB \Slot_LED_pad[4]  (
	.I(Slot[4]),
	.O(Slot_LED[4])
);
// @10:14
  OB \Slot_LED_pad[3]  (
	.I(Slot[3]),
	.O(Slot_LED[3])
);
// @10:14
  OB \Slot_LED_pad[2]  (
	.I(Slot[2]),
	.O(Slot_LED[2])
);
// @10:14
  OB \Slot_LED_pad[1]  (
	.I(Slot[1]),
	.O(Slot_LED[1])
);
// @10:14
  OB \Slot_LED_pad[0]  (
	.I(Slot[0]),
	.O(Slot_LED[0])
);
// @10:13
  OB Uart_Out_pad (
	.I(Uart_Out_c),
	.O(Uart_Out)
);
// @10:12
  IB Uart_In_pad (
	.I(Uart_In),
	.O(Uart_In_c)
);
// @10:11
  IB Clock_pad (
	.I(Clock),
	.O(Clock_c)
);
// @10:10
  IB Reset_pad (
	.I(Reset),
	.O(Reset_c)
);
assign S_Data = (DioSel & PCM_Din_c) | (DioSel & PCM_Din_c & ~PCM_Dout_c) | 
   (~DioSel & PCM_Dout_c) | (~DioSel & ~PCM_Din_c & PCM_Dout_c) | (PCM_Din_c & 
   PCM_Dout_c);
// @10:80
  UartSend u2 (
	.PCM_Data({PCM_Data[7], PCM_Data[6], PCM_Data[5], PCM_Data[4], PCM_Data[3], 
   PCM_Data[2], PCM_Data[1], PCM_Data[0]}),
	.DioSel(DioSel),
	.GND(GND),
	.WrClock(WrClock),
	.VCC(VCC),
	.Uart_Out_c(Uart_Out_c),
	.Reset_c(Reset_c),
	.CLK_TXD(CLK_TXD)
);
// @10:90
  BaudR U3 (
	.GND(GND),
	.CLK_TXD(CLK_TXD),
	.Clock_c(Clock_c),
	.Reset_c(Reset_c),
	.CLK_RXD(CLK_RXD)
);
// @10:98
  UartRec u4 (
	.GetComm({GetComm[8], GetComm[7], GetComm[6], GetComm[5], GetComm[4], 
   GetComm[3], GetComm[2], GetComm[1], GetComm[0]}),
	.Uart_In_c_i(Uart_In_c_i),
	.VCC(VCC),
	.Uart_In_c(Uart_In_c),
	.Reset_c(Reset_c),
	.CLK_RXD(CLK_RXD),
	.GND(GND),
	.GetDataPC(GetDataPC)
);
// @10:107
  PCM U5 (
	.PCM_Data({PCM_Data[7], PCM_Data[6], PCM_Data[5], PCM_Data[4], PCM_Data[3], 
   PCM_Data[2], PCM_Data[1], PCM_Data[0]}),
	.Slot({Slot[7], Slot[6], Slot[5], Slot[4], Slot[3], Slot[2], Slot[1], 
   Slot[0]}),
	.WrClock(WrClock),
	.VCC(VCC),
	.Reset_c(Reset_c),
	.PCM_CLK_c_i(PCM_CLK_c_i),
	.S_Data(S_Data),
	.GND(GND),
	.PCM_Fsync_c(PCM_Fsync_c)
);
  assign GND_Z = 1'b0;
  assign VCC_Z = 1'b1;
  TSALL TSALL_INST (
	.TSALL(GND_Z)
);
endmodule /* GetPcm */