getpcm.vm

PCM数据采集

	.SP(un8_rstate),
	.CK(CLK_RXD),
	.Q(recbuffer[1])
);
// @7:39
  FD1P3AX \recbuffer_Z[2]  (
	.D(recbuffer[3]),
	.SP(un8_rstate),
	.CK(CLK_RXD),
	.Q(recbuffer[2])
);
// @7:39
  FD1P3AX \recbuffer_Z[3]  (
	.D(recbuffer[4]),
	.SP(un8_rstate),
	.CK(CLK_RXD),
	.Q(recbuffer[3])
);
// @7:39
  FD1P3AX \recbuffer_Z[4]  (
	.D(recbuffer[5]),
	.SP(un8_rstate),
	.CK(CLK_RXD),
	.Q(recbuffer[4])
);
// @7:39
  FD1P3AX \recbuffer_Z[5]  (
	.D(recbuffer[6]),
	.SP(un8_rstate),
	.CK(CLK_RXD),
	.Q(recbuffer[5])
);
// @7:39
  FD1P3AX \recbuffer_Z[6]  (
	.D(recbuffer[7]),
	.SP(un8_rstate),
	.CK(CLK_RXD),
	.Q(recbuffer[6])
);
// @7:39
  FD1P3AX \recbuffer_Z[7]  (
	.D(recbuffer[8]),
	.SP(un8_rstate),
	.CK(CLK_RXD),
	.Q(recbuffer[7])
);
// @7:39
  FD1P3AX \recbuffer_Z[8]  (
	.D(Uart_In_c),
	.SP(un8_rstate),
	.CK(CLK_RXD),
	.Q(recbuffer[8])
);
// @7:28
  FD1S3DX Start_Z (
	.D(VCC),
	.CK(Uart_In_c_i),
	.CD(GetDataPC_i),
	.Q(Start)
);
defparam Start_Z.GSR="DISABLED";
// @7:39
  FD1P3AY GetData_Z (
	.D(Start_i),
	.SP(N_23_i),
	.CK(CLK_RXD),
	.Q(GetData)
);
// @7:39
  FD1P3AX \DataRec_Z[0]  (
	.D(recbuffer[0]),
	.SP(un13_rstate),
	.CK(CLK_RXD),
	.Q(GetComm[0])
);
// @7:39
  FD1P3AX \DataRec_Z[1]  (
	.D(recbuffer[1]),
	.SP(un13_rstate),
	.CK(CLK_RXD),
	.Q(GetComm[1])
);
// @7:39
  FD1P3AX \DataRec_Z[2]  (
	.D(recbuffer[2]),
	.SP(un13_rstate),
	.CK(CLK_RXD),
	.Q(GetComm[2])
);
// @7:39
  FD1P3AX \DataRec_Z[3]  (
	.D(recbuffer[3]),
	.SP(un13_rstate),
	.CK(CLK_RXD),
	.Q(GetComm[3])
);
// @7:39
  FD1P3AX \DataRec_Z[4]  (
	.D(recbuffer[4]),
	.SP(un13_rstate),
	.CK(CLK_RXD),
	.Q(GetComm[4])
);
// @7:39
  FD1P3AX \DataRec_Z[5]  (
	.D(recbuffer[5]),
	.SP(un13_rstate),
	.CK(CLK_RXD),
	.Q(GetComm[5])
);
// @7:39
  FD1P3AX \DataRec_Z[6]  (
	.D(recbuffer[6]),
	.SP(un13_rstate),
	.CK(CLK_RXD),
	.Q(GetComm[6])
);
// @7:39
  FD1P3AX \DataRec_Z[7]  (
	.D(recbuffer[7]),
	.SP(un13_rstate),
	.CK(CLK_RXD),
	.Q(GetComm[7])
);
// @7:39
  FD1P3AX \DataRec_Z[8]  (
	.D(recbuffer[8]),
	.SP(un13_rstate),
	.CK(CLK_RXD),
	.Q(GetComm[8])
);
assign un23_rstate_p4 = (~rstate_3[3] & rstate_3[0] & rstate_3[1] & rstate_3[2]);
assign rstate_3[0] = (~Start & rstate[0]);
assign rstate_3[1] = (~Start & rstate[1]);
assign rstate_3[2] = (~Start & rstate[2]);
assign rstate_3[5] = (~Start & rstate[5]);
assign rstate_3[3] = (~Start & ~rstate[3]);
assign un23_rstate_axbxc4 = (Start & ~un23_rstate_p4) | (Start & ~rstate[4] & 
   ~un23_rstate_p4) | (rstate[4] & ~un23_rstate_p4) | (~Start & ~rstate[4] & 
   un23_rstate_p4);
assign un18_rstate_1 = (rstate[0] & rstate[1] & rstate[4] & rstate[5]);
assign un1_rstate_2_1 = (~rstate[1] & ~rstate[2] & ~rstate[4]);
assign un13_rstate_0 = (~rstate[0] & rstate[4] & rstate[5]);
assign un13_rstate = (rstate[2] & rstate[3] & rstate_3[1] & un13_rstate_0);
assign rstate_5[0] = (~rstate_3[3] & ~rstate_3[0]) | (~rstate_3[3] & ~rstate_3[0] & 
   ~rstate_3[5]) | (~rstate_3[0] & rstate_3[5]) | (~rstate_3[0] & ~un1_rstate_2_1) | 
   (~rstate_3[3] & ~rstate_3[0] & un1_rstate_2_1) | (~rstate_3[3] & ~rstate_3[0] & 
   ~rstate_3[5] & un1_rstate_2_1) | (rstate_3[3] & rstate_3[0] & ~rstate_3[5] & 
   un1_rstate_2_1) | (~rstate_3[0] & rstate_3[5] & un1_rstate_2_1);
assign un23_rstate_axbxc3 = (~rstate_3[3] & ~rstate_3[0]) | (~rstate_3[3] & 
   ~rstate_3[1]) | (~rstate_3[3] & ~rstate_3[0] & rstate_3[1]) | (~rstate_3[3] & 
   ~rstate_3[2]) | (~rstate_3[3] & ~rstate_3[0] & rstate_3[2]) | (~rstate_3[3] & 
   ~rstate_3[1] & rstate_3[2]) | (~rstate_3[3] & ~rstate_3[0] & rstate_3[1] & 
   rstate_3[2]) | (rstate_3[3] & rstate_3[0] & rstate_3[1] & rstate_3[2]);
assign N_23_i = (Start) | (Start & ~un18_rstate_1) | (Start & un18_rstate_1) | 
   (Start & ~rstate[3] & un18_rstate_1) | (Start & rstate[3] & un18_rstate_1) | 
   (Start & ~rstate[2] & rstate[3] & un18_rstate_1) | (rstate[2] & rstate[3] & 
   un18_rstate_1);
//@10:98
  assign NN_1 = 1'b0;
  assign NN_2 = 1'b1;
assign GetDataPC = GetData;
endmodule /* UartRec */

module PCM (
  PCM_Data,
  Slot,
  WrClock,
  VCC,
  Reset_c,
  PCM_CLK_c_i,
  S_Data,
  GND,
  PCM_Fsync_c
)
;
output [7:0] PCM_Data ;
input [7:0] Slot ;
output WrClock ;
input VCC ;
input Reset_c ;
input PCM_CLK_c_i ;
input S_Data ;
input GND ;
input PCM_Fsync_c ;
wire WrClock ;
wire VCC ;
wire Reset_c ;
wire PCM_CLK_c_i ;
wire S_Data ;
wire GND ;
wire PCM_Fsync_c ;
wire [3:0] data_tmp;
wire [3:3] data_tmp_i;
wire [7:0] databuf;
wire [7:0] databuf_2;
wire [2:0] count;
wire [2:0] count_3;
wire [7:0] chunnel_3;
wire [7:0] databuf_QN;
wire [2:0] count_QN;
wire [7:0] chunnel;
wire [7:0] chunnel_QN;
wire [7:0] PCM_Data_QN;
wire [7:1] un16_chunnel_a_4;
wire un12_chunnel ;
wire lastfsync ;
wire L_Data_1_sqmuxa_i ;
wire un1_chunnel_cry_0_0_S0 ;
wire N_32 ;
wire un1_chunnel_cry_6_0_S1 ;
wire un1_chunnel_cry_6_0_S0 ;
wire un1_chunnel_cry_4_0_S1 ;
wire un1_chunnel_cry_4_0_S0 ;
wire un1_chunnel_cry_2_0_S1 ;
wire un1_chunnel_cry_2_0_S0 ;
wire un1_chunnel_cry_0_0_S1 ;
wire un2_fsync_i ;
wire lastfsync_QN ;
wire L_Data ;
wire L_Data_QN ;
wire un2_fsync ;
wire un2_count ;
wire I_19_0_S0 ;
wire I_19_0_S1 ;
wire N_28 ;
wire I_1_0_S1 ;
wire un1_chunnel_cry_5 ;
wire un1_chunnel_cry_6 ;
wire un1_chunnel_cry_6_0_COUT1 ;
wire un1_chunnel_cry_3 ;
wire un1_chunnel_cry_4 ;
wire un1_chunnel_cry_1 ;
wire un1_chunnel_cry_2 ;
wire un1_chunnel_cry_0 ;
wire un16_chunnel_a_4_cry_5 ;
wire un16_chunnel_a_4_cry_6 ;
wire un16_chunnel_a_4_cry_6_0_COUT1 ;
wire un16_chunnel_a_4_cry_3 ;
wire un16_chunnel_a_4_cry_4 ;
wire un16_chunnel_a_4_cry_1 ;
wire un16_chunnel_a_4_cry_2 ;
wire un16_chunnel_a_4_cry_0 ;
wire un16_chunnel_a_4_cry_0_0_S0 ;
wire NN_1 ;
wire NN_2 ;
// @4:61
  INV \un16_chunnel_0.data_tmp_i[3]  (
	.A(data_tmp[3]),
	.Z(data_tmp_i[3])
);
assign L_Data_1_sqmuxa_i = (un12_chunnel) | (un12_chunnel & ~PCM_Fsync_c) | 
   (un12_chunnel & PCM_Fsync_c) | (~lastfsync & PCM_Fsync_c) | (un12_chunnel & 
   lastfsync & PCM_Fsync_c);
assign databuf_2[0] = (databuf[0] & S_Data) | (databuf[0] & S_Data & ~lastfsync) | 
   (S_Data & lastfsync) | (S_Data & ~PCM_Fsync_c) | (databuf[0] & S_Data & 
   PCM_Fsync_c) | (databuf[0] & ~lastfsync & PCM_Fsync_c) | (S_Data & 
   lastfsync & PCM_Fsync_c);
assign N_32 = (~Slot[0] & PCM_Fsync_c & ~lastfsync) | (~Slot[0] & ~un1_chunnel_cry_0_0_S0) | 
   (Slot[0] & ~PCM_Fsync_c & un1_chunnel_cry_0_0_S0) | (Slot[0] & ~PCM_Fsync_c & 
   ~lastfsync & un1_chunnel_cry_0_0_S0) | (~Slot[0] & PCM_Fsync_c & ~lastfsync & 
   un1_chunnel_cry_0_0_S0) | (Slot[0] & lastfsync & un1_chunnel_cry_0_0_S0);
assign databuf_2[1] = (databuf[1] & databuf[0]) | (databuf[1] & databuf[0] & 
   ~lastfsync) | (databuf[0] & lastfsync) | (databuf[0] & ~PCM_Fsync_c) | 
   (databuf[1] & databuf[0] & PCM_Fsync_c) | (databuf[1] & ~lastfsync & 
   PCM_Fsync_c) | (databuf[0] & lastfsync & PCM_Fsync_c);
assign databuf_2[2] = (databuf[2] & databuf[1]) | (databuf[2] & databuf[1] & 
   ~lastfsync) | (databuf[1] & lastfsync) | (databuf[1] & ~PCM_Fsync_c) | 
   (databuf[2] & databuf[1] & PCM_Fsync_c) | (databuf[2] & ~lastfsync & 
   PCM_Fsync_c) | (databuf[1] & lastfsync & PCM_Fsync_c);
assign databuf_2[3] = (databuf[3] & databuf[2]) | (databuf[3] & databuf[2] & 
   ~lastfsync) | (databuf[2] & lastfsync) | (databuf[2] & ~PCM_Fsync_c) | 
   (databuf[3] & databuf[2] & PCM_Fsync_c) | (databuf[3] & ~lastfsync & 
   PCM_Fsync_c) | (databuf[2] & lastfsync & PCM_Fsync_c);
assign databuf_2[4] = (databuf[4] & databuf[3]) | (databuf[4] & databuf[3] & 
   ~lastfsync) | (databuf[3] & lastfsync) | (databuf[3] & ~PCM_Fsync_c) | 
   (databuf[4] & databuf[3] & PCM_Fsync_c) | (databuf[4] & ~lastfsync & 
   PCM_Fsync_c) | (databuf[3] & lastfsync & PCM_Fsync_c);
assign databuf_2[5] = (databuf[5] & databuf[4]) | (databuf[5] & databuf[4] & 
   ~lastfsync) | (databuf[4] & lastfsync) | (databuf[4] & ~PCM_Fsync_c) | 
   (databuf[5] & databuf[4] & PCM_Fsync_c) | (databuf[5] & ~lastfsync & 
   PCM_Fsync_c) | (databuf[4] & lastfsync & PCM_Fsync_c);
assign databuf_2[6] = (databuf[6] & databuf[5]) | (databuf[6] & databuf[5] & 
   ~lastfsync) | (databuf[5] & lastfsync) | (databuf[5] & ~PCM_Fsync_c) | 
   (databuf[6] & databuf[5] & PCM_Fsync_c) | (databuf[6] & ~lastfsync & 
   PCM_Fsync_c) | (databuf[5] & lastfsync & PCM_Fsync_c);
assign databuf_2[7] = (databuf[7] & databuf[6]) | (databuf[7] & databuf[6] & 
   ~lastfsync) | (databuf[6] & lastfsync) | (databuf[6] & ~PCM_Fsync_c) | 
   (databuf[7] & databuf[6] & PCM_Fsync_c) | (databuf[7] & ~lastfsync & 
   PCM_Fsync_c) | (databuf[6] & lastfsync & PCM_Fsync_c);
assign count_3[1] = (count[1] & ~count[0] & lastfsync) | (~count[1] & count[0] & 
   lastfsync) | (count[1] & ~count[0] & ~PCM_Fsync_c) | (~count[1] & count[0] & 
   ~PCM_Fsync_c) | (count[1] & ~count[0] & lastfsync & PCM_Fsync_c) | 
   (~count[1] & count[0] & lastfsync & PCM_Fsync_c);
assign count_3[0] = (~count[0] & lastfsync) | (~count[0] & ~PCM_Fsync_c) | 
   (~count[0] & lastfsync & PCM_Fsync_c);
assign chunnel_3[7] = (un1_chunnel_cry_6_0_S1 & lastfsync) | (un1_chunnel_cry_6_0_S1 & 
   ~PCM_Fsync_c) | (un1_chunnel_cry_6_0_S1 & lastfsync & PCM_Fsync_c);
assign chunnel_3[6] = (un1_chunnel_cry_6_0_S0 & lastfsync) | (un1_chunnel_cry_6_0_S0 & 
   ~PCM_Fsync_c) | (un1_chunnel_cry_6_0_S0 & lastfsync & PCM_Fsync_c);
assign chunnel_3[5] = (un1_chunnel_cry_4_0_S1 & lastfsync) | (un1_chunnel_cry_4_0_S1 & 
   ~PCM_Fsync_c) | (un1_chunnel_cry_4_0_S1 & lastfsync & PCM_Fsync_c);
assign chunnel_3[4] = (un1_chunnel_cry_4_0_S0 & lastfsync) | (un1_chunnel_cry_4_0_S0 & 
   ~PCM_Fsync_c) | (un1_chunnel_cry_4_0_S0 & lastfsync & PCM_Fsync_c);
assign chunnel_3[3] = (un1_chunnel_cry_2_0_S1 & lastfsync) | (un1_chunnel_cry_2_0_S1 & 
   ~PCM_Fsync_c) | (un1_chunnel_cry_2_0_S1 & lastfsync & PCM_Fsync_c);
assign chunnel_3[2] = (un1_chunnel_cry_2_0_S0 & lastfsync) | (un1_chunnel_cry_2_0_S0 & 
   ~PCM_Fsync_c) | (un1_chunnel_cry_2_0_S0 & lastfsync & PCM_Fsync_c);
assign chunnel_3[1] = (un1_chunnel_cry_0_0_S1 & lastfsync) | (un1_chunnel_cry_0_0_S1 & 
   ~PCM_Fsync_c) | (un1_chunnel_cry_0_0_S1 & lastfsync & PCM_Fsync_c);
assign un2_fsync_i = (lastfsync) | (~PCM_Fsync_c) | (lastfsync & PCM_Fsync_c);
// @4:61
  FD1S3AX lastfsync_Z (
	.D(PCM_Fsync_c),
	.CK(PCM_CLK_c_i),
	.Q(lastfsync)
);
// @4:61
  FD1P3AX \databuf_Z[0]  (
	.D(S_Data),
	.SP(un2_fsync_i),
	.CK(PCM_CLK_c_i),
	.Q(databuf[0])
);
// @4:61
  FD1P3AX \databuf_Z[1]  (
	.D(databuf[0]),
	.SP(un2_fsync_i),
	.CK(PCM_CLK_c_i),
	.Q(databuf[1])
);
// @4:61
  FD1P3AX \databuf_Z[2]  (
	.D(databuf[1]),
	.SP(un2_fsync_i),
	.CK(PCM_CLK_c_i),
	.Q(databuf[2])
);
// @4:61
  FD1P3AX \databuf_Z[3]  (
	.D(databuf[2]),
	.SP(un2_fsync_i),
	.CK(PCM_CLK_c_i),
	.Q(databuf[3])
);
// @4:61
  FD1P3AX \databuf_Z[4]  (
	.D(databuf[3]),
	.SP(un2_fsync_i),
	.CK(PCM_CLK_c_i),
	.Q(databuf[4])
);
// @4:61
  FD1P3AX \databuf_Z[5]  (
	.D(databuf[4]),
	.SP(un2_fsync_i),
	.CK(PCM_CLK_c_i),
	.Q(databuf[5])
);
// @4:61
  FD1P3AX \databuf_Z[6]  (
	.D(databuf[5]),
	.SP(un2_fsync_i),
	.CK(PCM_CLK_c_i),
	.Q(databuf[6])
);
// @4:61
  FD1P3AX \databuf_Z[7]  (
	.D(databuf[6]),
	.SP(un2_fsync_i),
	.CK(PCM_CLK_c_i),
	.Q(databuf[7])
);
// @4:61
  FD1S3AX \count_Z[0]  (
	.D(count_3[0]),
	.CK(PCM_CLK_c_i),
	.Q(count[0])
);
// @4:61
  FD1S3AX \count_Z[1]  (
	.D(count_3[1]),
	.CK(PCM_CLK_c_i),
	.Q(count[1])
);
// @4:61
  FD1S3AX \count_Z[2]  (
	.D(count_3[2]),
	.CK(PCM_CLK_c_i),
	.Q(count[2])
);
// @4:61
  FD1S3AX \chunnel_Z[0]  (
	.D(chunnel_3[0]),
	.CK(PCM_CLK_c_i),
	.Q(chunnel[0])
);
// @4:61
  FD1S3AX \chunnel_Z[1]  (
	.D(chunnel_3[1]),
	.CK(PCM_CLK_c_i),
	.Q(chunnel[1])
);
// @4:61
  FD1S3AX \chunnel_Z[2]  (
	.D(chunnel_3[2]),
	.CK(PCM_CLK_c_i),
	.Q(chunnel[2])
);
// @4:61
  FD1S3AX \chunnel_Z[3]  (
	.D(chunnel_3[3]),
	.CK(PCM_CLK_c_i),
	.Q(chunnel[3])
);
// @4:61
  FD1S3AX \chunnel_Z[4]  (
	.D(chunnel_3[4]),
	.CK(PCM_CLK_c_i),
	.Q(chunnel[4])
);
// @4:61
  FD1S3AX \chunnel_Z[5]  (
	.D(chunnel_3[5]),
	.CK(PCM_CLK_c_i),
	.Q(chunnel[5])
);
// @4:61
  FD1S3AX \chunnel_Z[6]  (
	.D(chunnel_3[6]),
	.CK(PCM_CLK_c_i),
	.Q(chunnel[6])
);
// @4:61
  FD1S3AX \chunnel_Z[7]  (
	.D(chunnel_3[7]),
	.CK(PCM_CLK_c_i),
	.Q(chunnel[7])
);
// @4:61
  FD1P3AX \PCM_Data_Z[0]  (
	.D(databuf_2[0]),
	.SP(un12_chunnel),
	.CK(PCM_CLK_c_i),
	.Q(PCM_Data[0])
);
// @4:61
  FD1P3AX \PCM_Data_Z[1]  (
	.D(databuf_2[1]),
	.SP(un12_chunnel),
	.CK(PCM_CLK_c_i),
	.Q(PCM_Data[1])
);
// @4:61
  FD1P3AX \PCM_Data_Z[2]  (
	.D(databuf_2[2]),
	.SP(un12_chunnel),
	.CK(PCM_CLK_c_i),
	.Q(PCM_Data[2])
);
// @4:61
  FD1P3AX \PCM_Data_Z[3]  (
	.D(databuf_2[3]),
	.SP(un12_chunnel),
	.CK(PCM_CLK_c_i),
	.Q(PCM_Data[3])
);
// @4:61
  FD1P3AX \PCM_Data_Z[4]  (
	.D(databuf_2[4]),
	.SP(un12_chunnel),
	.CK(PCM_CLK_c_i),
	.Q(PCM_Data[4])
);
// @4:61
  FD1P3AX \PCM_Data_Z[5]  (
	.D(databuf_2[5]),
	.SP(un12_chunnel),
	.CK(PCM_CLK_c_i),
	.Q(PCM_Data[5])
);
// @4:61
  FD1P3AX \PCM_Data_Z[6]  (
	.D(databuf_2[6]),
	.SP(un12_chunnel),
	.CK(PCM_CLK_c_i),
	.Q(PCM_Data[6])
);
// @4:61
  FD1P3AX \PCM_Data_Z[7]  (
	.D(databuf_2[7]),
	.SP(un12_chunnel),
	.CK(PCM_CLK_c_i),
	.Q(PCM_Data[7])
);
// @4:61
  FD1P3AX L_Data_Z (