getpcm.vm

PCM数据采集

//
// Written by Synplify
// Product Version "Version 8.8L2"
// Program "Synplify", Mapper "8.8.0, Build 018R"
// Fri Jun 20 12:38:52 2008
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\isptools7_0\synpbase\lib\vhd\std.vhd "
// file 2 "\d:\isptools7_0\ispcpld\..\cae_library\synthesis\vhdl\machxo.vhd "
// file 3 "\d:\isptools7_0\synpbase\lib\vhd\std1164.vhd "
// file 4 "\d:\cpld\getpcm~1\pcm.vhd "
// file 5 "\d:\isptools7_0\synpbase\lib\vhd\unsigned.vhd "
// file 6 "\d:\isptools7_0\synpbase\lib\vhd\arith.vhd "
// file 7 "\d:\cpld\getpcm~1\uartrec.vhd "
// file 8 "\d:\cpld\getpcm~1\baudr.vhd "
// file 9 "\d:\cpld\getpcm~1\uartsend.vhd "
// file 10 "\d:\cpld\getpcm~1\getpcm.vhd "

`timescale 100 ps/100 ps
module UartSend (
  PCM_Data,
  DioSel,
  GND,
  WrClock,
  VCC,
  Uart_Out_c,
  Reset_c,
  CLK_TXD
)
;
input [7:0] PCM_Data ;
input DioSel ;
input GND ;
input WrClock ;
input VCC ;
output Uart_Out_c ;
input Reset_c ;
input CLK_TXD ;
wire DioSel ;
wire GND ;
wire WrClock ;
wire VCC ;
wire Uart_Out_c ;
wire Reset_c ;
wire CLK_TXD ;
wire [3:0] tstate;
wire [3:0] tstate_QN;
wire [7:0] sendbuffer_4;
wire [8:0] sendbuffer;
wire [8:0] sendbuffer_QN;
wire Start ;
wire Start_i ;
wire N_34_i ;
wire sendbuffer10_i ;
wire tstate_n2 ;
wire N_6_i ;
wire tstate_n1 ;
wire tstate_n3 ;
wire N_30_i ;
wire UartOut_2 ;
wire UartOut_QN ;
wire N_36_i ;
wire Start_QN_0 ;
wire UartBusy ;
wire SendComp_QN ;
wire un1_tstate_1 ;
wire N_8 ;
wire NN_1 ;
wire NN_2 ;
// @4:61
  INV Start_i_cZ (
	.A(Start),
	.Z(Start_i)
);
assign N_34_i = (Start) | (Start & ~tstate[3]) | (tstate[3]) | (Start & 
   ~tstate[2]) | (Start & ~tstate[3] & ~tstate[2]) | (tstate[3] & ~tstate[2]) | 
   (tstate[2]) | (Start & ~tstate[1]) | (Start & ~tstate[3] & ~tstate[1]) | 
   (tstate[3] & ~tstate[1]) | (Start & ~tstate[2] & ~tstate[1]) | (Start & 
   ~tstate[3] & ~tstate[2] & ~tstate[1]) | (tstate[3] & ~tstate[2] & ~tstate[1]) | 
   (tstate[2] & ~tstate[1]) | (tstate[1]);
assign sendbuffer10_i = (Start) | (Start & ~tstate[1]) | (Start & ~tstate[2] & 
   ~tstate[1]) | (~tstate[3] & ~tstate[2] & ~tstate[1]) | (Start & tstate[3] & 
   ~tstate[2] & ~tstate[1]) | (Start & tstate[2] & ~tstate[1]) | (Start & 
   tstate[1]);
assign tstate_n2 = (Start) | (tstate[2] & ~tstate[1]) | (tstate[2] & ~Start & 
   ~tstate[1]) | (Start & ~tstate[1]) | (Start & tstate[1]) | (tstate[2] & 
   ~tstate[0]) | (tstate[2] & ~Start & ~tstate[0]) | (Start & ~tstate[0]) | 
   (Start & tstate[0]) | (tstate[2] & ~tstate[1] & tstate[0]) | (tstate[2] & 
   ~Start & ~tstate[1] & tstate[0]) | (Start & ~tstate[1] & tstate[0]) | 
   (~tstate[2] & tstate[1] & tstate[0]) | (~tstate[2] & ~Start & tstate[1] & 
   tstate[0]) | (Start & tstate[1] & tstate[0]);
// @9:38
  FD1P3AX \tstate_Z[0]  (
	.D(N_6_i),
	.SP(N_34_i),
	.CK(CLK_TXD),
	.Q(tstate[0])
);
// @9:38
  FD1P3AX \tstate_Z[1]  (
	.D(tstate_n1),
	.SP(N_34_i),
	.CK(CLK_TXD),
	.Q(tstate[1])
);
// @9:38
  FD1P3AX \tstate_Z[2]  (
	.D(tstate_n2),
	.SP(N_34_i),
	.CK(CLK_TXD),
	.Q(tstate[2])
);
// @9:38
  FD1P3AX \tstate_Z[3]  (
	.D(tstate_n3),
	.SP(N_34_i),
	.CK(CLK_TXD),
	.Q(tstate[3])
);
// @9:38
  FD1P3AX \sendbuffer_Z[0]  (
	.D(sendbuffer_4[0]),
	.SP(N_34_i),
	.CK(CLK_TXD),
	.Q(sendbuffer[0])
);
// @9:38
  FD1P3AX \sendbuffer_Z[1]  (
	.D(sendbuffer_4[1]),
	.SP(N_34_i),
	.CK(CLK_TXD),
	.Q(sendbuffer[1])
);
// @9:38
  FD1P3AX \sendbuffer_Z[2]  (
	.D(sendbuffer_4[2]),
	.SP(N_34_i),
	.CK(CLK_TXD),
	.Q(sendbuffer[2])
);
// @9:38
  FD1P3AX \sendbuffer_Z[3]  (
	.D(sendbuffer_4[3]),
	.SP(N_34_i),
	.CK(CLK_TXD),
	.Q(sendbuffer[3])
);
// @9:38
  FD1P3AX \sendbuffer_Z[4]  (
	.D(sendbuffer_4[4]),
	.SP(N_34_i),
	.CK(CLK_TXD),
	.Q(sendbuffer[4])
);
// @9:38
  FD1P3AX \sendbuffer_Z[5]  (
	.D(sendbuffer_4[5]),
	.SP(N_34_i),
	.CK(CLK_TXD),
	.Q(sendbuffer[5])
);
// @9:38
  FD1P3AX \sendbuffer_Z[6]  (
	.D(sendbuffer_4[6]),
	.SP(N_34_i),
	.CK(CLK_TXD),
	.Q(sendbuffer[6])
);
// @9:38
  FD1P3AX \sendbuffer_Z[7]  (
	.D(sendbuffer_4[7]),
	.SP(N_34_i),
	.CK(CLK_TXD),
	.Q(sendbuffer[7])
);
// @9:38
  FD1P3AX \sendbuffer_Z[8]  (
	.D(N_30_i),
	.SP(N_34_i),
	.CK(CLK_TXD),
	.Q(sendbuffer[8])
);
// @9:38
  FD1S3AY UartOut_Z (
	.D(UartOut_2),
	.CK(CLK_TXD),
	.Q(Uart_Out_c)
);
// @9:26
  FD1S3DX Start_Z (
	.D(VCC),
	.CK(WrClock),
	.CD(N_36_i),
	.Q(Start)
);
defparam Start_Z.GSR="DISABLED";
// @9:38
  FD1P3AY SendComp_Z (
	.D(Start_i),
	.SP(sendbuffer10_i),
	.CK(CLK_TXD),
	.Q(UartBusy)
);
assign sendbuffer_4[7] = (PCM_Data[7] & Start) | (PCM_Data[7] & Start & 
   ~sendbuffer[8]) | (PCM_Data[7] & sendbuffer[8]) | (~Start & sendbuffer[8]) | 
   (PCM_Data[7] & Start & sendbuffer[8]);
assign sendbuffer_4[6] = (PCM_Data[6] & Start) | (PCM_Data[6] & Start & 
   ~sendbuffer[7]) | (PCM_Data[6] & sendbuffer[7]) | (~Start & sendbuffer[7]) | 
   (PCM_Data[6] & Start & sendbuffer[7]);
assign sendbuffer_4[5] = (PCM_Data[5] & Start) | (PCM_Data[5] & Start & 
   ~sendbuffer[6]) | (PCM_Data[5] & sendbuffer[6]) | (~Start & sendbuffer[6]) | 
   (PCM_Data[5] & Start & sendbuffer[6]);
assign sendbuffer_4[4] = (PCM_Data[4] & Start) | (PCM_Data[4] & Start & 
   ~sendbuffer[5]) | (PCM_Data[4] & sendbuffer[5]) | (~Start & sendbuffer[5]) | 
   (PCM_Data[4] & Start & sendbuffer[5]);
assign sendbuffer_4[3] = (PCM_Data[3] & Start) | (PCM_Data[3] & Start & 
   ~sendbuffer[4]) | (PCM_Data[3] & sendbuffer[4]) | (~Start & sendbuffer[4]) | 
   (PCM_Data[3] & Start & sendbuffer[4]);
assign sendbuffer_4[2] = (PCM_Data[2] & Start) | (PCM_Data[2] & Start & 
   ~sendbuffer[3]) | (PCM_Data[2] & sendbuffer[3]) | (~Start & sendbuffer[3]) | 
   (PCM_Data[2] & Start & sendbuffer[3]);
assign sendbuffer_4[1] = (PCM_Data[1] & Start) | (PCM_Data[1] & Start & 
   ~sendbuffer[2]) | (PCM_Data[1] & sendbuffer[2]) | (~Start & sendbuffer[2]) | 
   (PCM_Data[1] & Start & sendbuffer[2]);
assign sendbuffer_4[0] = (PCM_Data[0] & Start) | (PCM_Data[0] & Start & 
   ~sendbuffer[1]) | (PCM_Data[0] & sendbuffer[1]) | (~Start & sendbuffer[1]) | 
   (PCM_Data[0] & Start & sendbuffer[1]);
assign N_30_i = (DioSel) | (~Start) | (DioSel & Start);
assign N_6_i = (Start) | (~tstate[0]) | (Start & tstate[0]);
assign N_36_i = (~Reset_c) | (~UartBusy) | (~Reset_c & UartBusy);
assign tstate_n1 = (Start) | (Start & ~tstate[1]) | (Start & ~tstate[0] & 
   ~tstate[1]) | (tstate[0] & ~tstate[1]) | (Start & tstate[1]) | (~tstate[0] & 
   tstate[1]) | (Start & tstate[0] & tstate[1]);
assign un1_tstate_1 = (~tstate[1] & ~tstate[2] & ~tstate[3]);
assign N_8 = (~Start & tstate[0] & tstate[1]);
assign tstate_n3 = (N_8 & Start & tstate[2]) | (N_8 & tstate[2] & ~tstate[3]) | 
   (~N_8 & ~Start & tstate[3]) | (~Start & ~tstate[2] & tstate[3]) | (~N_8 & 
   ~Start & tstate[2] & tstate[3]) | (N_8 & Start & tstate[2] & tstate[3]);
assign UartOut_2 = (~Start & sendbuffer[0]) | (~Start & sendbuffer[0] & 
   ~un1_tstate_1) | (~Start & un1_tstate_1);
  assign NN_1 = 1'b0;
  assign NN_2 = 1'b1;
endmodule /* UartSend */

module BaudR (
  GND,
  CLK_TXD,
  Clock_c,
  Reset_c,
  CLK_RXD
)
;
input GND ;
output CLK_TXD ;
input Clock_c ;
input Reset_c ;
output CLK_RXD ;
wire GND ;
wire CLK_TXD ;
wire Clock_c ;
wire Reset_c ;
wire CLK_RXD ;
wire [5:0] count;
wire [0:0] count_i;
wire [2:0] count_QN_0;
wire [1:1] \Get_CLK_TXD.count ;
wire [5:0] count_3;
wire [0:0] count_0;
wire [1:0] count_QN_1;
wire [5:3] count_QN;
wire CLK_RXD_i ;
wire SUM1 ;
wire un8_count_axbxc2 ;
wire un8_count_axbxc3 ;
wire un8_count_axbxc4 ;
wire un4_count ;
wire CLK_RXD_QN ;
wire un8_count_p4 ;
wire un4_count_1 ;
wire NN_1 ;
wire VCC ;
// @4:61
  INV \Get_CLK_TXD.count_i[0]  (
	.A(count[0]),
	.Z(count_i[0])
);
// @4:61
  INV CLK_RXD_i_cZ (
	.A(CLK_RXD),
	.Z(CLK_RXD_i)
);
// @8:37
  FD1S3AX \Get_CLK_TXD.count_Z[0]  (
	.D(count_i[0]),
	.CK(CLK_RXD),
	.Q(count[0])
);
// @8:37
  FD1S3AX \Get_CLK_TXD.count_Z[1]  (
	.D(SUM1),
	.CK(CLK_RXD),
	.Q(\Get_CLK_TXD.count [1])
);
// @8:21
  FD1S3AX \Get_CLK_RXD.count_Z[0]  (
	.D(count_3[0]),
	.CK(Clock_c),
	.Q(count_0[0])
);
// @8:21
  FD1S3AX \Get_CLK_RXD.count_Z[1]  (
	.D(count_3[1]),
	.CK(Clock_c),
	.Q(count[1])
);
// @8:21
  FD1S3AX \Get_CLK_RXD.count_Z[2]  (
	.D(un8_count_axbxc2),
	.CK(Clock_c),
	.Q(count[2])
);
// @8:21
  FD1S3AX \Get_CLK_RXD.count_Z[3]  (
	.D(un8_count_axbxc3),
	.CK(Clock_c),
	.Q(count[3])
);
// @8:21
  FD1S3AX \Get_CLK_RXD.count_Z[4]  (
	.D(un8_count_axbxc4),
	.CK(Clock_c),
	.Q(count[4])
);
// @8:21
  FD1S3AX \Get_CLK_RXD.count_Z[5]  (
	.D(count_3[5]),
	.CK(Clock_c),
	.Q(count[5])
);
// @8:21
  FD1P3AX CLK_RXD_Z (
	.D(CLK_RXD_i),
	.SP(un4_count),
	.CK(Clock_c),
	.Q(CLK_RXD)
);
assign un8_count_p4 = (count_0[0] & count[1] & count[2] & count[3]);
assign SUM1 = (\Get_CLK_TXD.count [1] & ~count[0]) | (~\Get_CLK_TXD.count [1] & 
   count[0]);
assign un8_count_axbxc4 = (count[4] & ~un8_count_p4) | (~count[4] & un8_count_p4);
assign un4_count_1 = (~count[2] & ~count[4]);
assign un8_count_axbxc2 = (count_0[0] & count[1] & ~count[2]) | (~count_0[0] & 
   count[2]) | (~count[1] & count[2]) | (~count_0[0] & count[1] & count[2]);
assign un8_count_axbxc3 = (count_0[0] & count[1] & count[2] & ~count[3]) | 
   (~count_0[0] & count[3]) | (~count[1] & count[3]) | (~count_0[0] & 
   count[1] & count[3]) | (~count[2] & count[3]) | (~count_0[0] & count[2] & 
   count[3]) | (~count[1] & count[2] & count[3]) | (~count_0[0] & count[1] & 
   count[2] & count[3]);
assign un4_count = (count[1] & ~count[3] & count[5] & un4_count_1);
assign count_3[5] = (~count[4] & count[5] & ~un4_count) | (count[5] & ~un4_count & 
   ~un8_count_p4) | (count[4] & ~count[5] & ~un4_count & un8_count_p4) | 
   (~count[4] & count[5] & ~un4_count & un8_count_p4);
assign count_3[0] = (~count_0[0] & ~un4_count);
assign count_3[1] = (count_0[0] & ~count[1] & ~un4_count) | (~count_0[0] & 
   count[1] & ~un4_count);
//@10:90
//@10:90
  assign NN_1 = 1'b0;
  assign VCC = 1'b1;
assign CLK_TXD = \Get_CLK_TXD.count [1];
endmodule /* BaudR */

module UartRec (
  GetComm,
  Uart_In_c_i,
  VCC,
  Uart_In_c,
  Reset_c,
  CLK_RXD,
  GND,
  GetDataPC
)
;
output [8:0] GetComm ;
input Uart_In_c_i ;
input VCC ;
input Uart_In_c ;
input Reset_c ;
input CLK_RXD ;
input GND ;
output GetDataPC ;
wire Uart_In_c_i ;
wire VCC ;
wire Uart_In_c ;
wire Reset_c ;
wire CLK_RXD ;
wire GND ;
wire GetDataPC ;
wire [5:0] rstate;
wire [5:0] rstate_3;
wire [0:0] rstate_5;
wire [5:0] rstate_QN;
wire [8:0] recbuffer;
wire [8:0] recbuffer_QN;
wire [8:0] DataRec_QN;
wire GetDataPC_i ;
wire Start ;
wire Start_i ;
wire un23_rstate_p4 ;
wire un23_rstate_axbxc5 ;
wire un23_rstate_axbxc2 ;
wire un23_rstate_axbxc1 ;
wire un8_rstate ;
wire un23_rstate_axbxc3 ;
wire un23_rstate_axbxc4 ;
wire Start_QN ;
wire N_23_i ;
wire GetData ;
wire GetData_QN ;
wire un13_rstate ;
wire un18_rstate_1 ;
wire un1_rstate_2_1 ;
wire un13_rstate_0 ;
wire NN_1 ;
wire NN_2 ;
// @4:61
  INV GetDataPC_i_cZ (
	.A(GetData),
	.Z(GetDataPC_i)
);
// @4:61
  INV Start_i_cZ (
	.A(Start),
	.Z(Start_i)
);
assign un23_rstate_axbxc5 = (un23_rstate_p4 & Start) | (un23_rstate_p4 & 
   rstate[4] & ~rstate[5]) | (un23_rstate_p4 & rstate[4] & ~Start & ~rstate[5]) | 
   (un23_rstate_p4 & Start & ~rstate[5]) | (un23_rstate_p4 & ~rstate[4] & 
   rstate[5]) | (~un23_rstate_p4 & ~Start & rstate[5]) | (~rstate[4] & 
   ~Start & rstate[5]) | (~un23_rstate_p4 & rstate[4] & ~Start & rstate[5]) | 
   (un23_rstate_p4 & Start & rstate[5]);
assign un23_rstate_axbxc2 = (rstate_3[1] & rstate_3[0] & ~rstate[2]) | 
   (rstate_3[1] & rstate_3[0] & ~rstate[2] & ~Start) | (~rstate_3[1] & 
   rstate[2] & ~Start) | (~rstate_3[0] & rstate[2] & ~Start) | (~rstate_3[1] & 
   rstate_3[0] & rstate[2] & ~Start) | (rstate_3[1] & rstate_3[0] & Start);
assign un23_rstate_axbxc1 = (rstate_3[0] & ~rstate[1]) | (rstate_3[0] & 
   ~rstate[1] & ~Start) | (~rstate_3[0] & rstate[1] & ~Start) | (rstate_3[0] & 
   Start);
assign un8_rstate = (~rstate[1] & rstate[0] & ~Start);
// @7:39
  FD1S3AX \rstate_Z[0]  (
	.D(rstate_5[0]),
	.CK(CLK_RXD),
	.Q(rstate[0])
);
// @7:39
  FD1S3AX \rstate_Z[1]  (
	.D(un23_rstate_axbxc1),
	.CK(CLK_RXD),
	.Q(rstate[1])
);
// @7:39
  FD1S3AX \rstate_Z[2]  (
	.D(un23_rstate_axbxc2),
	.CK(CLK_RXD),
	.Q(rstate[2])
);
// @7:39
  FD1S3AX \rstate_Z[3]  (
	.D(un23_rstate_axbxc3),
	.CK(CLK_RXD),
	.Q(rstate[3])
);
// @7:39
  FD1S3AX \rstate_Z[4]  (
	.D(un23_rstate_axbxc4),
	.CK(CLK_RXD),
	.Q(rstate[4])
);
// @7:39
  FD1S3AX \rstate_Z[5]  (
	.D(un23_rstate_axbxc5),
	.CK(CLK_RXD),
	.Q(rstate[5])
);
// @7:39
  FD1P3AX \recbuffer_Z[0]  (
	.D(recbuffer[1]),
	.SP(un8_rstate),
	.CK(CLK_RXD),
	.Q(recbuffer[0])
);
// @7:39
  FD1P3AX \recbuffer_Z[1]  (
	.D(recbuffer[2]),