pcm.vm

PCM数据采集

//
// Written by Synplify
// Product Version "Version 8.8L2"
// Program "Synplify", Mapper "8.8.0, Build 018R"
// Thu Jun 19 11:12:50 2008
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\isptools7_0\synpbase\lib\vhd\std.vhd "
// file 2 "\d:\isptools7_0\ispcpld\..\cae_library\synthesis\vhdl\xp2.vhd "
// file 3 "\d:\isptools7_0\synpbase\lib\vhd\std1164.vhd "
// file 4 "\d:\cpld\fpga\getpcm\pcm.vhd "
// file 5 "\d:\isptools7_0\synpbase\lib\vhd\unsigned.vhd "
// file 6 "\d:\isptools7_0\synpbase\lib\vhd\arith.vhd "

`timescale 100 ps/100 ps
module PCM (
  Reset,
  PCLK,
  S_Data,
  FSYNC,
  Slot,
  PCM_Data,
  L_Data
)
;
input Reset ;
input PCLK ;
input S_Data ;
input FSYNC ;
input [7:0] Slot ;
output [7:0] PCM_Data ;
output L_Data ;
wire Reset ;
wire PCLK ;
wire S_Data ;
wire FSYNC ;
wire L_Data ;
wire [2:0] count;
wire [7:0] databuf;
wire [7:0] chunnel;
wire [2:0] \un7_chunnel_0.data_tmp ;
wire [6:0] chunnel_cry;
wire [7:0] chunnel_s;
wire [7:0] chunnel_lm;
wire [0:0] chunnel_cry_0_S0;
wire [7:7] chunnel_s_0_S1;
wire [7:7] chunnel_s_0_COUT;
wire [7:0] Slot_c;
wire [7:0] PCM_Data_c;
wire [7:0] chunnel_QN;
wire [2:0] count_QN;
wire [7:1] databuf_QN;
wire lastfsync ;
wire un1_fsync_0_a2 ;
wire I_28_0_S1 ;
wire un2_chunnel_0_a2 ;
wire count_n0 ;
wire N_6 ;
wire N_10 ;
wire un7_chunnel_a_4_p4 ;
wire un7_chunnel_a_4_p7 ;
wire un7_chunnel_a_4_c2 ;
wire un7_chunnel_a_4_ac0_7 ;
wire un1_fsync_i ;
wire N_15_i ;
wire N_12_i ;
wire \un7_chunnel_0.I_14_0  ;
wire \un7_chunnel_0.I_23_0  ;
wire \un7_chunnel_0.I_32_0  ;
wire \un7_chunnel_0.I_33_0  ;
wire I_1_0_S0 ;
wire I_1_0_S1 ;
wire I_10_0_S0 ;
wire I_10_0_S1 ;
wire I_28_0_S0 ;
wire I_28_0_COUT ;
wire L_Data_1_sqmuxa_i_s_1 ;
wire un7_chunnel_a_4_p7_sx ;
wire un7_chunnel_a_4_p4_x ;
wire GND ;
wire VCC ;
wire Reset_c ;
wire PCLK_c ;
wire S_Data_c ;
wire FSYNC_c ;
wire L_Data_c ;
wire lastfsync_QN ;
wire PCLK_c_i ;
wire GND_Z ;
wire VCC_Z ;
  PUR PUR_INST (
	.PUR(VCC)
);
  VHI VCC_0 (
	.Z(VCC)
);
  VLO GND_0 (
	.Z(GND)
);
  INV PCLK_c_i_cZ (
	.A(PCLK_c),
	.Z(PCLK_c_i)
);
assign N_12_i = (count[1] & ~count[0] & lastfsync) | (~count[1] & count[0] & 
   lastfsync) | (count[1] & ~count[0] & ~FSYNC_c) | (~count[1] & count[0] & 
   ~FSYNC_c) | (count[1] & ~count[0] & lastfsync & FSYNC_c) | (~count[1] & 
   count[0] & lastfsync & FSYNC_c);
assign chunnel_lm[7] = (chunnel_s[7] & lastfsync) | (chunnel_s[7] & ~FSYNC_c) | 
   (chunnel_s[7] & lastfsync & FSYNC_c);
assign chunnel_lm[6] = (chunnel_s[6] & lastfsync) | (chunnel_s[6] & ~FSYNC_c) | 
   (chunnel_s[6] & lastfsync & FSYNC_c);
assign chunnel_lm[5] = (chunnel_s[5] & lastfsync) | (chunnel_s[5] & ~FSYNC_c) | 
   (chunnel_s[5] & lastfsync & FSYNC_c);
assign chunnel_lm[4] = (chunnel_s[4] & lastfsync) | (chunnel_s[4] & ~FSYNC_c) | 
   (chunnel_s[4] & lastfsync & FSYNC_c);
assign chunnel_lm[3] = (chunnel_s[3] & lastfsync) | (chunnel_s[3] & ~FSYNC_c) | 
   (chunnel_s[3] & lastfsync & FSYNC_c);
assign chunnel_lm[2] = (chunnel_s[2] & lastfsync) | (chunnel_s[2] & ~FSYNC_c) | 
   (chunnel_s[2] & lastfsync & FSYNC_c);
assign chunnel_lm[1] = (chunnel_s[1] & lastfsync) | (chunnel_s[1] & ~FSYNC_c) | 
   (chunnel_s[1] & lastfsync & FSYNC_c);
assign chunnel_lm[0] = (chunnel_s[0] & lastfsync) | (chunnel_s[0] & ~FSYNC_c) | 
   (chunnel_s[0] & lastfsync & FSYNC_c);
assign count_n0 = (~count[0] & lastfsync) | (~count[0] & ~FSYNC_c) | (~count[0] & 
   lastfsync & FSYNC_c);
// @4:61
  IFS1P3DX \databuf_0io_Z[0]  (
	.D(S_Data_c),
	.SP(un1_fsync_i),
	.SCLK(PCLK_c_i),
	.CD(GND),
	.Q(databuf[0])
);
// @4:61
  OFS1P3DX \PCM_Data_0io_Z[0]  (
	.D(databuf[0]),
	.SP(un2_chunnel_0_a2),
	.SCLK(PCLK_c_i),
	.CD(GND),
	.Q(PCM_Data_c[0])
);
// @4:61
  OFS1P3DX \PCM_Data_0io_Z[1]  (
	.D(databuf[1]),
	.SP(un2_chunnel_0_a2),
	.SCLK(PCLK_c_i),
	.CD(GND),
	.Q(PCM_Data_c[1])
);
// @4:61
  OFS1P3DX \PCM_Data_0io_Z[2]  (
	.D(databuf[2]),
	.SP(un2_chunnel_0_a2),
	.SCLK(PCLK_c_i),
	.CD(GND),
	.Q(PCM_Data_c[2])
);
// @4:61
  OFS1P3DX \PCM_Data_0io_Z[3]  (
	.D(databuf[3]),
	.SP(un2_chunnel_0_a2),
	.SCLK(PCLK_c_i),
	.CD(GND),
	.Q(PCM_Data_c[3])
);
// @4:61
  OFS1P3DX \PCM_Data_0io_Z[4]  (
	.D(databuf[4]),
	.SP(un2_chunnel_0_a2),
	.SCLK(PCLK_c_i),
	.CD(GND),
	.Q(PCM_Data_c[4])
);
// @4:61
  OFS1P3DX \PCM_Data_0io_Z[5]  (
	.D(databuf[5]),
	.SP(un2_chunnel_0_a2),
	.SCLK(PCLK_c_i),
	.CD(GND),
	.Q(PCM_Data_c[5])
);
// @4:61
  OFS1P3DX \PCM_Data_0io_Z[6]  (
	.D(databuf[6]),
	.SP(un2_chunnel_0_a2),
	.SCLK(PCLK_c_i),
	.CD(GND),
	.Q(PCM_Data_c[6])
);
// @4:61
  OFS1P3DX \PCM_Data_0io_Z[7]  (
	.D(databuf[7]),
	.SP(un2_chunnel_0_a2),
	.SCLK(PCLK_c_i),
	.CD(GND),
	.Q(PCM_Data_c[7])
);
// @4:61
  OFS1P3DX L_Data_0io_Z (
	.D(un1_fsync_i),
	.SP(N_6),
	.SCLK(PCLK_c_i),
	.CD(GND),
	.Q(L_Data_c)
);
// @4:61
  FD1S3AX lastfsync_Z (
	.D(FSYNC_c),
	.CK(PCLK_c_i),
	.Q(lastfsync)
);
// @4:61
  FD1P3AX \databuf_Z[1]  (
	.D(databuf[0]),
	.SP(un1_fsync_i),
	.CK(PCLK_c_i),
	.Q(databuf[1])
);
// @4:61
  FD1P3AX \databuf_Z[2]  (
	.D(databuf[1]),
	.SP(un1_fsync_i),
	.CK(PCLK_c_i),
	.Q(databuf[2])
);
// @4:61
  FD1P3AX \databuf_Z[3]  (
	.D(databuf[2]),
	.SP(un1_fsync_i),
	.CK(PCLK_c_i),
	.Q(databuf[3])
);
// @4:61
  FD1P3AX \databuf_Z[4]  (
	.D(databuf[3]),
	.SP(un1_fsync_i),
	.CK(PCLK_c_i),
	.Q(databuf[4])
);
// @4:61
  FD1P3AX \databuf_Z[5]  (
	.D(databuf[4]),
	.SP(un1_fsync_i),
	.CK(PCLK_c_i),
	.Q(databuf[5])
);
// @4:61
  FD1P3AX \databuf_Z[6]  (
	.D(databuf[5]),
	.SP(un1_fsync_i),
	.CK(PCLK_c_i),
	.Q(databuf[6])
);
// @4:61
  FD1P3AX \databuf_Z[7]  (
	.D(databuf[6]),
	.SP(un1_fsync_i),
	.CK(PCLK_c_i),
	.Q(databuf[7])
);
// @4:61
  FD1S3AX \count_Z[0]  (
	.D(count_n0),
	.CK(PCLK_c_i),
	.Q(count[0])
);
// @4:61
  FD1S3AX \count_Z[1]  (
	.D(N_12_i),
	.CK(PCLK_c_i),
	.Q(count[1])
);
// @4:61
  FD1S3AX \count_Z[2]  (
	.D(N_15_i),
	.CK(PCLK_c_i),
	.Q(count[2])
);
// @4:61
  FD1P3AX \chunnel_Z[0]  (
	.D(chunnel_lm[0]),
	.SP(N_10),
	.CK(PCLK_c_i),
	.Q(chunnel[0])
);
// @4:61
  FD1P3AX \chunnel_Z[1]  (
	.D(chunnel_lm[1]),
	.SP(N_10),
	.CK(PCLK_c_i),
	.Q(chunnel[1])
);
// @4:61
  FD1P3AX \chunnel_Z[2]  (
	.D(chunnel_lm[2]),
	.SP(N_10),
	.CK(PCLK_c_i),
	.Q(chunnel[2])
);
// @4:61
  FD1P3AX \chunnel_Z[3]  (
	.D(chunnel_lm[3]),
	.SP(N_10),
	.CK(PCLK_c_i),
	.Q(chunnel[3])
);
// @4:61
  FD1P3AX \chunnel_Z[4]  (
	.D(chunnel_lm[4]),
	.SP(N_10),
	.CK(PCLK_c_i),
	.Q(chunnel[4])
);
// @4:61
  FD1P3AX \chunnel_Z[5]  (
	.D(chunnel_lm[5]),
	.SP(N_10),
	.CK(PCLK_c_i),
	.Q(chunnel[5])
);
// @4:61
  FD1P3AX \chunnel_Z[6]  (
	.D(chunnel_lm[6]),
	.SP(N_10),
	.CK(PCLK_c_i),
	.Q(chunnel[6])
);
// @4:61
  FD1P3AX \chunnel_Z[7]  (
	.D(chunnel_lm[7]),
	.SP(N_10),
	.CK(PCLK_c_i),
	.Q(chunnel[7])
);
  GSR GSR_INST (
	.GSR(Reset_c)
);
// @4:14
  OB L_Data_pad (
	.I(L_Data_c),
	.O(L_Data)
);
// @4:13
  OB \PCM_Data_pad[7]  (
	.I(PCM_Data_c[7]),
	.O(PCM_Data[7])
);
// @4:13
  OB \PCM_Data_pad[6]  (
	.I(PCM_Data_c[6]),
	.O(PCM_Data[6])
);
// @4:13
  OB \PCM_Data_pad[5]  (
	.I(PCM_Data_c[5]),
	.O(PCM_Data[5])
);
// @4:13
  OB \PCM_Data_pad[4]  (
	.I(PCM_Data_c[4]),
	.O(PCM_Data[4])
);
// @4:13
  OB \PCM_Data_pad[3]  (
	.I(PCM_Data_c[3]),
	.O(PCM_Data[3])
);
// @4:13
  OB \PCM_Data_pad[2]  (
	.I(PCM_Data_c[2]),
	.O(PCM_Data[2])
);
// @4:13
  OB \PCM_Data_pad[1]  (
	.I(PCM_Data_c[1]),
	.O(PCM_Data[1])
);
// @4:13
  OB \PCM_Data_pad[0]  (
	.I(PCM_Data_c[0]),
	.O(PCM_Data[0])
);
// @4:12
  IB \Slot_pad[7]  (
	.I(Slot[7]),
	.O(Slot_c[7])
);
// @4:12
  IB \Slot_pad[6]  (
	.I(Slot[6]),
	.O(Slot_c[6])
);
// @4:12
  IB \Slot_pad[5]  (
	.I(Slot[5]),
	.O(Slot_c[5])
);
// @4:12
  IB \Slot_pad[4]  (
	.I(Slot[4]),
	.O(Slot_c[4])
);
// @4:12
  IB \Slot_pad[3]  (
	.I(Slot[3]),
	.O(Slot_c[3])
);
// @4:12
  IB \Slot_pad[2]  (
	.I(Slot[2]),
	.O(Slot_c[2])
);
// @4:12
  IB \Slot_pad[1]  (
	.I(Slot[1]),
	.O(Slot_c[1])
);
// @4:12
  IB \Slot_pad[0]  (
	.I(Slot[0]),
	.O(Slot_c[0])
);
// @4:11
  IB FSYNC_pad (
	.I(FSYNC),
	.O(FSYNC_c)
);
// @4:10
  IB S_Data_pad (
	.I(S_Data),
	.O(S_Data_c)
);
// @4:9
  IB PCLK_pad (
	.I(PCLK),
	.O(PCLK_c)
);
// @4:8
  IB Reset_pad (
	.I(Reset),
	.O(Reset_c)
);
assign un7_chunnel_a_4_p4 = (Slot_c[0] & Slot_c[1] & Slot_c[2] & Slot_c[3]);
assign un1_fsync_0_a2 = (FSYNC_c & ~lastfsync);
assign un7_chunnel_a_4_c2 = (Slot_c[0] & Slot_c[1]);
assign \un7_chunnel_0.I_14_0  = (Slot_c[3] & ~chunnel[3]) | (~Slot_c[3] & 
   chunnel[3]);
assign \un7_chunnel_0.I_23_0  = (Slot_c[5] & ~chunnel[5]) | (~Slot_c[5] & 
   chunnel[5]);
assign \un7_chunnel_0.I_32_0  = (Slot_c[7] & ~chunnel[7]) | (~Slot_c[7] & 
   chunnel[7]);
assign \un7_chunnel_0.I_33_0  = (Slot_c[6] & ~chunnel[6]) | (~Slot_c[6] & 
   chunnel[6]);
assign N_10 = (count[0] & count[1] & count[2]) | (count[0] & count[1] & 
   count[2] & ~un1_fsync_0_a2) | (un1_fsync_0_a2);
assign un2_chunnel_0_a2 = (~count[0] & ~count[1] & ~count[2] & I_28_0_S1);
assign N_15_i = (count[0] & count[1] & ~count[2] & ~un1_fsync_0_a2) | (~count[0] & 
   count[2] & ~un1_fsync_0_a2) | (~count[1] & count[2] & ~un1_fsync_0_a2) | 
   (~count[0] & count[1] & count[2] & ~un1_fsync_0_a2);
assign L_Data_1_sqmuxa_i_s_1 = (~count[0] & ~count[1]);
assign N_6 = (un1_fsync_0_a2) | (un1_fsync_0_a2 & ~I_28_0_S1) | (L_Data_1_sqmuxa_i_s_1 & 
   ~count[2] & I_28_0_S1) | (L_Data_1_sqmuxa_i_s_1 & ~count[2] & ~un1_fsync_0_a2 & 
   I_28_0_S1) | (un1_fsync_0_a2 & I_28_0_S1);
assign un7_chunnel_a_4_p7_sx = (~Slot_c[0]) | (~Slot_c[2]) | (~Slot_c[0] & 
   Slot_c[2]) | (~Slot_c[3]) | (~Slot_c[0] & Slot_c[3]) | (~Slot_c[2] & 
   Slot_c[3]) | (~Slot_c[0] & Slot_c[2] & Slot_c[3]) | (~Slot_c[6]) | 
   (~Slot_c[0] & Slot_c[6]) | (~Slot_c[2] & Slot_c[6]) | (~Slot_c[0] & 
   Slot_c[2] & Slot_c[6]) | (~Slot_c[3] & Slot_c[6]) | (~Slot_c[0] & Slot_c[3] & 
   Slot_c[6]) | (~Slot_c[2] & Slot_c[3] & Slot_c[6]) | (~Slot_c[0] & Slot_c[2] & 
   Slot_c[3] & Slot_c[6]);
assign un7_chunnel_a_4_p7 = (Slot_c[1] & Slot_c[4] & Slot_c[5] & ~un7_chunnel_a_4_p7_sx);
assign un7_chunnel_a_4_p4_x = (Slot_c[1] & Slot_c[2] & Slot_c[3]);
assign un7_chunnel_a_4_ac0_7 = (un7_chunnel_a_4_p4_x & Slot_c[0] & Slot_c[4] & 
   Slot_c[5]);
assign un1_fsync_i = (lastfsync) | (~FSYNC_c) | (lastfsync & FSYNC_c);
  CCU2B \un7_chunnel_0.I_28_0  (
	.A0(\un7_chunnel_0.I_32_0 ),
	.B0(\un7_chunnel_0.I_33_0 ),
	.C0(un7_chunnel_a_4_ac0_7),
	.D0(un7_chunnel_a_4_p7),
	.A1(GND),
	.B1(GND),
	.C1(GND),
	.D1(VCC),
	.CIN(\un7_chunnel_0.data_tmp [2]),
	.COUT(I_28_0_COUT),
	.S0(I_28_0_S0),
	.S1(I_28_0_S1)
);
defparam \un7_chunnel_0.I_28_0 .INIT0=16'h8241;
defparam \un7_chunnel_0.I_28_0 .INIT1=16'h0a0c;
defparam \un7_chunnel_0.I_28_0 .INJECT1_0="YES";
defparam \un7_chunnel_0.I_28_0 .INJECT1_1="NO";
  CCU2B \un7_chunnel_0.I_10_0  (
	.A0(Slot_c[2]),
	.B0(chunnel[2]),
	.C0(\un7_chunnel_0.I_14_0 ),
	.D0(un7_chunnel_a_4_c2),
	.A1(Slot_c[4]),
	.B1(chunnel[4]),
	.C1(\un7_chunnel_0.I_23_0 ),
	.D1(un7_chunnel_a_4_p4),
	.CIN(\un7_chunnel_0.data_tmp [0]),
	.COUT(\un7_chunnel_0.data_tmp [2]),
	.S0(I_10_0_S0),
	.S1(I_10_0_S1)
);
defparam \un7_chunnel_0.I_10_0 .INIT0=16'h2409;
defparam \un7_chunnel_0.I_10_0 .INIT1=16'h2409;
defparam \un7_chunnel_0.I_10_0 .INJECT1_0="YES";
defparam \un7_chunnel_0.I_10_0 .INJECT1_1="YES";
  CCU2B \un7_chunnel_0.I_1_0  (
	.A0(GND),
	.B0(VCC),
	.C0(GND),
	.D0(VCC),
	.A1(Slot_c[0]),
	.B1(Slot_c[1]),
	.C1(chunnel[0]),
	.D1(chunnel[1]),
	.CIN(GND),
	.COUT(\un7_chunnel_0.data_tmp [0]),
	.S0(I_1_0_S0),
	.S1(I_1_0_S1)
);
defparam \un7_chunnel_0.I_1_0 .INIT0=16'h0a0c;
defparam \un7_chunnel_0.I_1_0 .INIT1=16'h4218;
defparam \un7_chunnel_0.I_1_0 .INJECT1_0="NO";
defparam \un7_chunnel_0.I_1_0 .INJECT1_1="YES";
// @4:61
  CCU2B \chunnel_s_0[7]  (
	.A0(chunnel[7]),
	.B0(GND),
	.C0(GND),
	.D0(VCC),
	.A1(GND),
	.B1(GND),
	.C1(GND),
	.D1(VCC),
	.CIN(chunnel_cry[6]),
	.COUT(chunnel_s_0_COUT[7]),
	.S0(chunnel_s[7]),
	.S1(chunnel_s_0_S1[7])
);
defparam \chunnel_s_0[7] .INIT0=16'h060a;
defparam \chunnel_s_0[7] .INIT1=16'h0a0c;
defparam \chunnel_s_0[7] .INJECT1_0="NO";
defparam \chunnel_s_0[7] .INJECT1_1="NO";
// @4:61
  CCU2B \chunnel_cry_0[5]  (
	.A0(chunnel[5]),
	.B0(GND),
	.C0(GND),
	.D0(VCC),
	.A1(chunnel[6]),
	.B1(GND),
	.C1(GND),
	.D1(VCC),
	.CIN(chunnel_cry[4]),
	.COUT(chunnel_cry[6]),
	.S0(chunnel_s[5]),
	.S1(chunnel_s[6])
);
defparam \chunnel_cry_0[5] .INIT0=16'h0600;
defparam \chunnel_cry_0[5] .INIT1=16'h0600;
defparam \chunnel_cry_0[5] .INJECT1_0="NO";
defparam \chunnel_cry_0[5] .INJECT1_1="NO";
// @4:61
  CCU2B \chunnel_cry_0[3]  (
	.A0(chunnel[3]),
	.B0(GND),
	.C0(GND),
	.D0(VCC),
	.A1(chunnel[4]),
	.B1(GND),
	.C1(GND),
	.D1(VCC),
	.CIN(chunnel_cry[2]),
	.COUT(chunnel_cry[4]),
	.S0(chunnel_s[3]),
	.S1(chunnel_s[4])
);
defparam \chunnel_cry_0[3] .INIT0=16'h0600;
defparam \chunnel_cry_0[3] .INIT1=16'h0600;
defparam \chunnel_cry_0[3] .INJECT1_0="NO";
defparam \chunnel_cry_0[3] .INJECT1_1="NO";
// @4:61
  CCU2B \chunnel_cry_0[1]  (
	.A0(chunnel[1]),
	.B0(GND),
	.C0(GND),
	.D0(VCC),
	.A1(chunnel[2]),
	.B1(GND),
	.C1(GND),
	.D1(VCC),
	.CIN(chunnel_cry[0]),
	.COUT(chunnel_cry[2]),
	.S0(chunnel_s[1]),
	.S1(chunnel_s[2])
);
defparam \chunnel_cry_0[1] .INIT0=16'h0600;
defparam \chunnel_cry_0[1] .INIT1=16'h0600;
defparam \chunnel_cry_0[1] .INJECT1_0="NO";
defparam \chunnel_cry_0[1] .INJECT1_1="NO";
  CCU2B \chunnel_cry_0[0]  (
	.A0(GND),
	.B0(VCC),
	.C0(GND),
	.D0(VCC),
	.A1(chunnel[0]),
	.B1(GND),
	.C1(GND),
	.D1(VCC),
	.CIN(GND),
	.COUT(chunnel_cry[0]),
	.S0(chunnel_cry_0_S0[0]),
	.S1(chunnel_s[0])
);
defparam \chunnel_cry_0[0] .INIT0=16'h0a0c;
defparam \chunnel_cry_0[0] .INIT1=16'h0600;
defparam \chunnel_cry_0[0] .INJECT1_0="NO";
defparam \chunnel_cry_0[0] .INJECT1_1="NO";
  assign GND_Z = 1'b0;
  assign VCC_Z = 1'b1;
endmodule /* PCM */