uartsend.vm

PCM数据采集

//
// Written by Synplify
// Product Version "Version 8.8L2"
// Program "Synplify", Mapper "8.8.0, Build 018R"
// Thu Jun 19 21:20:44 2008
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\isptools7_0\synpbase\lib\vhd\std.vhd "
// file 2 "\d:\isptools7_0\ispcpld\..\cae_library\synthesis\vhdl\machxo.vhd "
// file 3 "\d:\isptools7_0\synpbase\lib\vhd\std1164.vhd "
// file 4 "\d:\cpld\getpcm~1\uartsend.vhd "
// file 5 "\d:\isptools7_0\synpbase\lib\vhd\arith.vhd "
// file 6 "\d:\isptools7_0\synpbase\lib\vhd\unsigned.vhd "

`timescale 100 ps/100 ps
module UartSend (
  Reset,
  SendClk,
  Data,
  Latch,
  UartOut,
  Busy
)
;
input Reset ;
input SendClk ;
input [8:0] Data ;
input Latch ;
output UartOut ;
output Busy ;
wire Reset ;
wire SendClk ;
wire Latch ;
wire UartOut ;
wire Busy ;
wire [3:0] tstate;
wire [8:0] sendbuffer;
wire [7:0] sendbuffer_4;
wire [8:0] Data_c;
wire [8:0] sendbuffer_QN;
wire [3:0] tstate_QN;
wire Start ;
wire UartOut_2 ;
wire tstate_n1 ;
wire tstate_n2 ;
wire tstate_n3 ;
wire un1_tstate_1 ;
wire N_8 ;
wire N_34_i ;
wire N_36_i ;
wire N_6_i ;
wire N_30_i ;
wire uartout7_i ;
wire GND ;
wire VCC ;
wire Reset_c ;
wire SendClk_c ;
wire Latch_c ;
wire UartOut_c ;
wire Busy_c ;
wire SendComp_QN ;
wire Start_QN ;
wire UartOut_QN ;
wire Start_i ;
wire GND_Z ;
wire VCC_Z ;
  PUR PUR_INST (
	.PUR(VCC)
);
  VHI VCC_0 (
	.Z(VCC)
);
  VLO GND_0 (
	.Z(GND)
);
  INV Start_i_cZ (
	.A(Start),
	.Z(Start_i)
);
assign N_34_i = (Start) | (Start & ~tstate[3]) | (tstate[3]) | (Start & 
   ~tstate[2]) | (Start & ~tstate[3] & ~tstate[2]) | (tstate[3] & ~tstate[2]) | 
   (tstate[2]) | (Start & ~tstate[1]) | (Start & ~tstate[3] & ~tstate[1]) | 
   (tstate[3] & ~tstate[1]) | (Start & ~tstate[2] & ~tstate[1]) | (Start & 
   ~tstate[3] & ~tstate[2] & ~tstate[1]) | (tstate[3] & ~tstate[2] & ~tstate[1]) | 
   (tstate[2] & ~tstate[1]) | (tstate[1]);
assign uartout7_i = (Start) | (Start & ~tstate[1]) | (Start & ~tstate[2] & 
   ~tstate[1]) | (~tstate[3] & ~tstate[2] & ~tstate[1]) | (Start & tstate[3] & 
   ~tstate[2] & ~tstate[1]) | (Start & tstate[2] & ~tstate[1]) | (Start & 
   tstate[1]);
assign tstate_n2 = (Start) | (tstate[2] & ~tstate[1]) | (tstate[2] & ~Start & 
   ~tstate[1]) | (Start & ~tstate[1]) | (Start & tstate[1]) | (tstate[2] & 
   ~tstate[0]) | (tstate[2] & ~Start & ~tstate[0]) | (Start & ~tstate[0]) | 
   (Start & tstate[0]) | (tstate[2] & ~tstate[1] & tstate[0]) | (tstate[2] & 
   ~Start & ~tstate[1] & tstate[0]) | (Start & ~tstate[1] & tstate[0]) | 
   (~tstate[2] & tstate[1] & tstate[0]) | (~tstate[2] & ~Start & tstate[1] & 
   tstate[0]) | (Start & tstate[1] & tstate[0]);
// @4:38
  FD1P3AX \tstate_Z[0]  (
	.D(N_6_i),
	.SP(N_34_i),
	.CK(SendClk_c),
	.Q(tstate[0])
);
// @4:38
  FD1P3AX \tstate_Z[1]  (
	.D(tstate_n1),
	.SP(N_34_i),
	.CK(SendClk_c),
	.Q(tstate[1])
);
// @4:38
  FD1P3AX \tstate_Z[2]  (
	.D(tstate_n2),
	.SP(N_34_i),
	.CK(SendClk_c),
	.Q(tstate[2])
);
// @4:38
  FD1P3AX \tstate_Z[3]  (
	.D(tstate_n3),
	.SP(N_34_i),
	.CK(SendClk_c),
	.Q(tstate[3])
);
// @4:38
  FD1P3AX \sendbuffer_Z[0]  (
	.D(sendbuffer_4[0]),
	.SP(N_34_i),
	.CK(SendClk_c),
	.Q(sendbuffer[0])
);
// @4:38
  FD1P3AX \sendbuffer_Z[1]  (
	.D(sendbuffer_4[1]),
	.SP(N_34_i),
	.CK(SendClk_c),
	.Q(sendbuffer[1])
);
// @4:38
  FD1P3AX \sendbuffer_Z[2]  (
	.D(sendbuffer_4[2]),
	.SP(N_34_i),
	.CK(SendClk_c),
	.Q(sendbuffer[2])
);
// @4:38
  FD1P3AX \sendbuffer_Z[3]  (
	.D(sendbuffer_4[3]),
	.SP(N_34_i),
	.CK(SendClk_c),
	.Q(sendbuffer[3])
);
// @4:38
  FD1P3AX \sendbuffer_Z[4]  (
	.D(sendbuffer_4[4]),
	.SP(N_34_i),
	.CK(SendClk_c),
	.Q(sendbuffer[4])
);
// @4:38
  FD1P3AX \sendbuffer_Z[5]  (
	.D(sendbuffer_4[5]),
	.SP(N_34_i),
	.CK(SendClk_c),
	.Q(sendbuffer[5])
);
// @4:38
  FD1P3AX \sendbuffer_Z[6]  (
	.D(sendbuffer_4[6]),
	.SP(N_34_i),
	.CK(SendClk_c),
	.Q(sendbuffer[6])
);
// @4:38
  FD1P3AX \sendbuffer_Z[7]  (
	.D(sendbuffer_4[7]),
	.SP(N_34_i),
	.CK(SendClk_c),
	.Q(sendbuffer[7])
);
// @4:38
  FD1P3AX \sendbuffer_Z[8]  (
	.D(N_30_i),
	.SP(N_34_i),
	.CK(SendClk_c),
	.Q(sendbuffer[8])
);
// @4:38
  FD1S3AY UartOut_Z (
	.D(UartOut_2),
	.CK(SendClk_c),
	.Q(UartOut_c)
);
// @4:26
  FD1S3DX Start_Z (
	.D(VCC),
	.CK(Latch_c),
	.CD(N_36_i),
	.Q(Start)
);
defparam Start_Z.GSR="DISABLED";
// @4:38
  FD1P3AY SendComp_Z (
	.D(Start_i),
	.SP(uartout7_i),
	.CK(SendClk_c),
	.Q(Busy_c)
);
  GSR GSR_INST (
	.GSR(Reset_c)
);
// @4:14
  OB Busy_pad (
	.I(Busy_c),
	.O(Busy)
);
// @4:13
  OB UartOut_pad (
	.I(UartOut_c),
	.O(UartOut)
);
// @4:12
  IB Latch_pad (
	.I(Latch),
	.O(Latch_c)
);
// @4:11
  IB \Data_pad[8]  (
	.I(Data[8]),
	.O(Data_c[8])
);
// @4:11
  IB \Data_pad[7]  (
	.I(Data[7]),
	.O(Data_c[7])
);
// @4:11
  IB \Data_pad[6]  (
	.I(Data[6]),
	.O(Data_c[6])
);
// @4:11
  IB \Data_pad[5]  (
	.I(Data[5]),
	.O(Data_c[5])
);
// @4:11
  IB \Data_pad[4]  (
	.I(Data[4]),
	.O(Data_c[4])
);
// @4:11
  IB \Data_pad[3]  (
	.I(Data[3]),
	.O(Data_c[3])
);
// @4:11
  IB \Data_pad[2]  (
	.I(Data[2]),
	.O(Data_c[2])
);
// @4:11
  IB \Data_pad[1]  (
	.I(Data[1]),
	.O(Data_c[1])
);
// @4:11
  IB \Data_pad[0]  (
	.I(Data[0]),
	.O(Data_c[0])
);
// @4:10
  IB SendClk_pad (
	.I(SendClk),
	.O(SendClk_c)
);
// @4:9
  IB Reset_pad (
	.I(Reset),
	.O(Reset_c)
);
assign sendbuffer_4[7] = (Data_c[7] & Start) | (Data_c[7] & Start & ~sendbuffer[8]) | 
   (Data_c[7] & sendbuffer[8]) | (~Start & sendbuffer[8]) | (Data_c[7] & 
   Start & sendbuffer[8]);
assign sendbuffer_4[6] = (Data_c[6] & Start) | (Data_c[6] & Start & ~sendbuffer[7]) | 
   (Data_c[6] & sendbuffer[7]) | (~Start & sendbuffer[7]) | (Data_c[6] & 
   Start & sendbuffer[7]);
assign sendbuffer_4[5] = (Data_c[5] & Start) | (Data_c[5] & Start & ~sendbuffer[6]) | 
   (Data_c[5] & sendbuffer[6]) | (~Start & sendbuffer[6]) | (Data_c[5] & 
   Start & sendbuffer[6]);
assign sendbuffer_4[4] = (Data_c[4] & Start) | (Data_c[4] & Start & ~sendbuffer[5]) | 
   (Data_c[4] & sendbuffer[5]) | (~Start & sendbuffer[5]) | (Data_c[4] & 
   Start & sendbuffer[5]);
assign sendbuffer_4[3] = (Data_c[3] & Start) | (Data_c[3] & Start & ~sendbuffer[4]) | 
   (Data_c[3] & sendbuffer[4]) | (~Start & sendbuffer[4]) | (Data_c[3] & 
   Start & sendbuffer[4]);
assign sendbuffer_4[2] = (Data_c[2] & Start) | (Data_c[2] & Start & ~sendbuffer[3]) | 
   (Data_c[2] & sendbuffer[3]) | (~Start & sendbuffer[3]) | (Data_c[2] & 
   Start & sendbuffer[3]);
assign sendbuffer_4[1] = (Data_c[1] & Start) | (Data_c[1] & Start & ~sendbuffer[2]) | 
   (Data_c[1] & sendbuffer[2]) | (~Start & sendbuffer[2]) | (Data_c[1] & 
   Start & sendbuffer[2]);
assign sendbuffer_4[0] = (Data_c[0] & Start) | (Data_c[0] & Start & ~sendbuffer[1]) | 
   (Data_c[0] & sendbuffer[1]) | (~Start & sendbuffer[1]) | (Data_c[0] & 
   Start & sendbuffer[1]);
assign N_30_i = (Data_c[8]) | (~Start) | (Data_c[8] & Start);
assign N_6_i = (Start) | (~tstate[0]) | (Start & tstate[0]);
assign N_36_i = (~Reset_c) | (~Busy_c) | (~Reset_c & Busy_c);
assign tstate_n1 = (Start) | (Start & ~tstate[1]) | (Start & ~tstate[0] & 
   ~tstate[1]) | (tstate[0] & ~tstate[1]) | (Start & tstate[1]) | (~tstate[0] & 
   tstate[1]) | (Start & tstate[0] & tstate[1]);
assign un1_tstate_1 = (~tstate[1] & ~tstate[2] & ~tstate[3]);
assign N_8 = (~Start & tstate[0] & tstate[1]);
assign tstate_n3 = (N_8 & Start & tstate[2]) | (N_8 & tstate[2] & ~tstate[3]) | 
   (~N_8 & ~Start & tstate[3]) | (~Start & ~tstate[2] & tstate[3]) | (~N_8 & 
   ~Start & tstate[2] & tstate[3]) | (N_8 & Start & tstate[2] & tstate[3]);
assign UartOut_2 = (~Start & sendbuffer[0]) | (~Start & sendbuffer[0] & 
   ~un1_tstate_1) | (~Start & un1_tstate_1);
  assign GND_Z = 1'b0;
  assign VCC_Z = 1'b1;
  TSALL TSALL_INST (
	.TSALL(GND_Z)
);
endmodule /* UartSend */