baudr.vm

PCM数据采集

//
// Written by Synplify
// Product Version "Version 9.0L1"
// Program "Synplify", Mapper "9.0.0, Build 139R"
// Wed Jun 18 10:49:09 2008
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\isptools7_0\synpbase\lib\vhd\std.vhd "
// file 2 "\d:\isptools7_0\ispcpld\..\cae_library\synthesis\vhdl\xp2.vhd "
// file 3 "\d:\isptools7_0\synpbase\lib\vhd\std1164.vhd "
// file 4 "\d:\cpld\fpga\getpcm\baudr.vhd "
// file 5 "\d:\isptools7_0\synpbase\lib\vhd\unsigned.vhd "
// file 6 "\d:\isptools7_0\synpbase\lib\vhd\arith.vhd "

`timescale 100 ps/100 ps
module BaudR (
  Reset,
  Clock,
  CLK_RXD,
  CLK_TXD
)
;
input Reset ;
input Clock ;
output CLK_RXD ;
output CLK_TXD ;
wire Reset ;
wire Clock ;
wire CLK_RXD ;
wire CLK_TXD ;
wire [5:0] \Get_CLK_RXD.count ;
wire [0:0] \Get_CLK_TXD.count ;
wire [5:0] count_3;
wire [5:0] count_QN;
wire [1:0] count_QN_0;
wire [0:0] \Get_CLK_TXD.count_i ;
wire \Get_CLK_RXD.un4_count  ;
wire CLK_RXD_c ;
wire SUM1 ;
wire un8_count_axbxc2 ;
wire un8_count_axbxc3 ;
wire un8_count_axbxc4 ;
wire un8_count_p4 ;
wire \Get_CLK_RXD.un4_count_1_0  ;
wire GND ;
wire VCC ;
wire Reset_c ;
wire Clock_c ;
wire CLK_TXD_c ;
wire CLK_RXD_QN ;
wire CLK_RXD_c_i ;
wire GND_Z ;
wire VCC_Z ;
  PUR PUR_INST (
	.PUR(VCC)
);
  VHI VCC_0 (
	.Z(VCC)
);
  VLO GND_0 (
	.Z(GND)
);
  INV \Get_CLK_TXD.count_i_cZ[0]  (
	.A(\Get_CLK_TXD.count [0]),
	.Z(\Get_CLK_TXD.count_i [0])
);
  INV CLK_RXD_c_i_cZ (
	.A(CLK_RXD_c),
	.Z(CLK_RXD_c_i)
);
// @4:37
  FD1S3AX \Get_CLK_TXD.count_Z[0]  (
	.D(\Get_CLK_TXD.count_i [0]),
	.CK(CLK_RXD_c),
	.Q(\Get_CLK_TXD.count [0])
);
// @4:37
  FD1S3AX \Get_CLK_TXD.count_Z[1]  (
	.D(SUM1),
	.CK(CLK_RXD_c),
	.Q(CLK_TXD_c)
);
// @4:21
  FD1S3AX \Get_CLK_RXD.count_Z[0]  (
	.D(count_3[0]),
	.CK(Clock_c),
	.Q(\Get_CLK_RXD.count [0])
);
// @4:21
  FD1S3AX \Get_CLK_RXD.count_Z[1]  (
	.D(count_3[1]),
	.CK(Clock_c),
	.Q(\Get_CLK_RXD.count [1])
);
// @4:21
  FD1S3AX \Get_CLK_RXD.count_Z[2]  (
	.D(un8_count_axbxc2),
	.CK(Clock_c),
	.Q(\Get_CLK_RXD.count [2])
);
// @4:21
  FD1S3AX \Get_CLK_RXD.count_Z[3]  (
	.D(un8_count_axbxc3),
	.CK(Clock_c),
	.Q(\Get_CLK_RXD.count [3])
);
// @4:21
  FD1S3AX \Get_CLK_RXD.count_Z[4]  (
	.D(un8_count_axbxc4),
	.CK(Clock_c),
	.Q(\Get_CLK_RXD.count [4])
);
// @4:21
  FD1S3AX \Get_CLK_RXD.count_Z[5]  (
	.D(count_3[5]),
	.CK(Clock_c),
	.Q(\Get_CLK_RXD.count [5])
);
// @4:21
  FD1P3AX CLK_RXD_Z (
	.D(CLK_RXD_c_i),
	.SP(\Get_CLK_RXD.un4_count ),
	.CK(Clock_c),
	.Q(CLK_RXD_c)
);
  GSR GSR_INST (
	.GSR(Reset_c)
);
// @4:10
  OB CLK_TXD_pad (
	.I(CLK_TXD_c),
	.O(CLK_TXD)
);
// @4:9
  OB CLK_RXD_pad (
	.I(CLK_RXD_c),
	.O(CLK_RXD)
);
// @4:8
  IB Clock_pad (
	.I(Clock),
	.O(Clock_c)
);
// @4:7
  IB Reset_pad (
	.I(Reset),
	.O(Reset_c)
);
assign un8_count_p4 = (\Get_CLK_RXD.count [0] & \Get_CLK_RXD.count [1] & 
   \Get_CLK_RXD.count [2] & \Get_CLK_RXD.count [3]);
assign SUM1 = (\Get_CLK_TXD.count [0] & ~CLK_TXD_c) | (~\Get_CLK_TXD.count [0] & 
   CLK_TXD_c);
assign un8_count_axbxc4 = (\Get_CLK_RXD.count [4] & ~un8_count_p4) | (~\Get_CLK_RXD.count [4] & 
   un8_count_p4);
assign un8_count_axbxc2 = (\Get_CLK_RXD.count [0] & \Get_CLK_RXD.count [1] & 
   ~\Get_CLK_RXD.count [2]) | (~\Get_CLK_RXD.count [0] & \Get_CLK_RXD.count [2]) | 
   (~\Get_CLK_RXD.count [1] & \Get_CLK_RXD.count [2]) | (~\Get_CLK_RXD.count [0] & 
   \Get_CLK_RXD.count [1] & \Get_CLK_RXD.count [2]);
assign un8_count_axbxc3 = (\Get_CLK_RXD.count [0] & \Get_CLK_RXD.count [1] & 
   \Get_CLK_RXD.count [2] & ~\Get_CLK_RXD.count [3]) | (~\Get_CLK_RXD.count [0] & 
   \Get_CLK_RXD.count [3]) | (~\Get_CLK_RXD.count [1] & \Get_CLK_RXD.count [3]) | 
   (~\Get_CLK_RXD.count [0] & \Get_CLK_RXD.count [1] & \Get_CLK_RXD.count [3]) | 
   (~\Get_CLK_RXD.count [2] & \Get_CLK_RXD.count [3]) | (~\Get_CLK_RXD.count [0] & 
   \Get_CLK_RXD.count [2] & \Get_CLK_RXD.count [3]) | (~\Get_CLK_RXD.count [1] & 
   \Get_CLK_RXD.count [2] & \Get_CLK_RXD.count [3]) | (~\Get_CLK_RXD.count [0] & 
   \Get_CLK_RXD.count [1] & \Get_CLK_RXD.count [2] & \Get_CLK_RXD.count [3]);
assign count_3[0] = (~\Get_CLK_RXD.count [0] & ~\Get_CLK_RXD.un4_count );
assign count_3[1] = (\Get_CLK_RXD.count [0] & ~\Get_CLK_RXD.count [1] & ~\Get_CLK_RXD.un4_count ) | 
   (~\Get_CLK_RXD.count [0] & \Get_CLK_RXD.count [1] & ~\Get_CLK_RXD.un4_count );
assign \Get_CLK_RXD.un4_count_1_0  = (~\Get_CLK_RXD.count [4] & \Get_CLK_RXD.count [5]);
assign \Get_CLK_RXD.un4_count  = (\Get_CLK_RXD.count [1] & ~\Get_CLK_RXD.count [2] & 
   ~\Get_CLK_RXD.count [3] & \Get_CLK_RXD.un4_count_1_0 );
assign count_3[5] = (~\Get_CLK_RXD.count [4] & \Get_CLK_RXD.count [5] & ~\Get_CLK_RXD.un4_count ) | 
   (\Get_CLK_RXD.count [5] & ~\Get_CLK_RXD.un4_count  & ~un8_count_p4) | 
   (\Get_CLK_RXD.count [4] & ~\Get_CLK_RXD.count [5] & ~\Get_CLK_RXD.un4_count  & 
   un8_count_p4) | (~\Get_CLK_RXD.count [4] & \Get_CLK_RXD.count [5] & ~\Get_CLK_RXD.un4_count  & 
   un8_count_p4);
  assign GND_Z = 1'b0;
  assign VCC_Z = 1'b1;
endmodule /* BaudR */