📄 getpcm.log
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#Build: Synplify for Lattice 8.8L2, Build 008R, Dec 7 2006
#install: D:\ISPTOOLS7_0\SYNPBASE
#OS: Windows XP 5.1
#Hostname: STAR-PANCAT
#Implementation: GETPCM~1
#Fri Jun 20 12:38:50 2008
$ Start of Compile
#Fri Jun 20 12:38:50 2008
Synplicity VHDL Compiler, version 3.7.5, Build 159R, built Apr 13 2007
Copyright (C) 1994-2007, Synplicity Inc. All Rights Reserved
@N: CD720 :"D:\ISPTOOLS7_0\SYNPBASE\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"D:\cpld\GETPCM~1\getpcm.vhd":7:7:7:12|Top entity is set to GetPcm.
VHDL syntax check successful!
@N: CD630 :"D:\cpld\GETPCM~1\getpcm.vhd":7:7:7:12|Synthesizing work.getpcm.art_getpcm
@N: CD630 :"D:\cpld\GETPCM~1\pcm.vhd":6:7:6:9|Synthesizing work.pcm.art_pcm
Post processing for work.pcm.art_pcm
@N: CD630 :"D:\cpld\GETPCM~1\uartrec.vhd":6:7:6:13|Synthesizing work.uartrec.atr_uartrec
Post processing for work.uartrec.atr_uartrec
@N: CD630 :"D:\cpld\GETPCM~1\baudr.vhd":5:7:5:11|Synthesizing work.baudr.art_baudr
Post processing for work.baudr.art_baudr
@N: CL177 :"D:\cpld\GETPCM~1\baudr.vhd":37:1:37:2|Sharing sequential element CLK_TXD.
@N: CD630 :"D:\cpld\GETPCM~1\uartsend.vhd":6:7:6:14|Synthesizing work.uartsend.art_uartsend
Post processing for work.uartsend.art_uartsend
Post processing for work.getpcm.art_getpcm
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jun 20 12:38:50 2008
###########################################################]
Synplicity Generic Technology Mapper, Version 8.8.0, Build 018R, Built Apr 17 2007 19:29:01
Copyright (C) 1994-2007, Synplicity Inc. All Rights Reserved
Product Version Version 8.8L2
@N: MF249 |Running in 32-bit mode.
RTL optimization done.
Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 52MB)
@N:"d:\cpld\getpcm~1\uartsend.vhd":38:5:38:6|Found counter in view:work.UartSend(art_uartsend) inst tstate[3:0]
@N: MF179 :|Found 8 bit by 8 bit '==' comparator, 'un16_chunnel'
Automatic dissolve during optimization of view:work.BaudR(art_baudr) of un2_count_1(PM_ADDC__0_2_lcmxo640c)
Automatic dissolve during optimization of view:work.PCM(art_pcm) of un4_count_1(PM_ADDC__0_3_lcmxo640c)
Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 52MB)
Clock Buffers:
Inserting Clock buffer for port PCM_CLK, TNM=PCM_CLK
Inserting Clock buffer on net CLK_RXD, TNM=CLK_RXD
Inserting Clock buffer for port Clock, TNM=Clock
Inserting Clock buffer for port Uart_In, TNM=Uart_In
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 53MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 53MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 53MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 53MB)
Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 53MB)
Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 50MB peak: 53MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
------------------------------------------------------------
Net buffering Report for view:work.GetPcm(art_getpcm):
No nets needed buffering.
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 53MB)
Found clock GetPcm|Clock with period 1000.00ns
Found clock GetPcm|Uart_In with period 1000.00ns
Found clock GetPcm|PCM_CLK with period 1000.00ns
Found clock BaudR|Get_CLK_TXD.count_inferred_clock[1] with period 1000.00ns
Found clock BaudR|CLK_RXD_inferred_clock with period 1000.00ns
Found clock UartRec|GetData_inferred_clock with period 1000.00ns
Found clock PCM|L_Data_inferred_clock with period 1000.00ns
##### START OF TIMING REPORT #####[
# Timing Report written on Fri Jun 20 12:38:51 2008
#
Top view: GetPcm
Requested Frequency: 1.0 MHz
Wire load mode: top
Paths requested: 3
Constraint File(s):
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
Performance Summary
*******************
Worst slack in design: 991.732
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
--------------------------------------------------------------------------------------------------------------------------------------------------
BaudR|CLK_RXD_inferred_clock 1.0 MHz 246.0 MHz 1000.000 4.065 995.935 inferred Inferred_clkgroup_4
BaudR|Get_CLK_TXD.count_inferred_clock[1] 1.0 MHz 216.5 MHz 1000.000 4.619 995.381 inferred Inferred_clkgroup_2
GetPcm|Clock 1.0 MHz 252.7 MHz 1000.000 3.957 996.043 inferred Inferred_clkgroup_3
GetPcm|PCM_CLK 1.0 MHz 121.0 MHz 1000.000 8.268 991.732 inferred Inferred_clkgroup_6
UartRec|GetData_inferred_clock 1.0 MHz 213.0 MHz 1000.000 4.694 995.306 inferred Inferred_clkgroup_0
System 1.0 MHz 495.7 MHz 1000.000 2.017 997.983 system default_clkgroup
==================================================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
UartRec|GetData_inferred_clock UartRec|GetData_inferred_clock | 1000.000 995.306 | No paths - | No paths - | No paths -
UartRec|GetData_inferred_clock BaudR|Get_CLK_TXD.count_inferred_clock[1] | Diff grp - | No paths - | No paths - | No paths -
UartRec|GetData_inferred_clock GetPcm|PCM_CLK | No paths - | No paths - | Diff grp - | No paths -
PCM|L_Data_inferred_clock BaudR|Get_CLK_TXD.count_inferred_clock[1] | Diff grp - | No paths - | No paths - | No paths -
BaudR|Get_CLK_TXD.count_inferred_clock[1] BaudR|Get_CLK_TXD.count_inferred_clock[1] | 1000.000 995.381 | No paths - | No paths - | No paths -
GetPcm|Clock GetPcm|Clock | 1000.000 996.043 | No paths - | No paths - | No paths -
BaudR|CLK_RXD_inferred_clock UartRec|GetData_inferred_clock | Diff grp - | No paths - | No paths - | No paths -
BaudR|CLK_RXD_inferred_clock BaudR|CLK_RXD_inferred_clock | 1000.000 995.935 | No paths - | No paths - | No paths -
GetPcm|Uart_In BaudR|CLK_RXD_inferred_clock | No paths - | No paths - | No paths - | Diff grp -
GetPcm|PCM_CLK BaudR|Get_CLK_TXD.count_inferred_clock[1] | No paths - | No paths - | No paths - | Diff grp -
GetPcm|PCM_CLK GetPcm|PCM_CLK | No paths - | 1000.000 991.732 | No paths - | No paths -
================================================================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
Input Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
-------------------------------------------------------------------------------
Clock NA NA NA NA NA
PCM_CLK NA NA NA NA NA
PCM_Din System (rising) NA 0.000 996.589
PCM_Dout System (rising) NA 0.000 996.589
PCM_Fsync System (rising) NA 0.000 993.566
Reset System (rising) NA 0.000 997.983
Uart_In System (rising) NA 0.000 998.168
===============================================================================
Output Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
--------------------------------------------------------------------------------------------------------------------
DioSel_LED UartRec|GetData_inferred_clock (rising) NA 4.694 1000.000
Slot_LED[0] UartRec|GetData_inferred_clock (rising) NA 4.694 1000.000
Slot_LED[1] UartRec|GetData_inferred_clock (rising) NA 4.661 1000.000
Slot_LED[2] UartRec|GetData_inferred_clock (rising) NA 4.661 1000.000
Slot_LED[3] UartRec|GetData_inferred_clock (rising) NA 4.661 1000.000
Slot_LED[4] UartRec|GetData_inferred_clock (rising) NA 4.661 1000.000
Slot_LED[5] UartRec|GetData_inferred_clock (rising) NA 4.661 1000.000
Slot_LED[6] UartRec|GetData_inferred_clock (rising) NA 4.661 1000.000
Slot_LED[7] UartRec|GetData_inferred_clock (rising) NA 4.661 1000.000
Uart_Out BaudR|Get_CLK_TXD.count_inferred_clock[1] (rising) NA 4.619 1000.000
====================================================================================================================
##### END OF TIMING REPORT #####]
---------------------------------------
Resource Usage Report
Part: lcmxo640c-5
Register bits: 89 of 640 (14%)
I/O cells: 17
Details:
CCU2: 10
FD1P3AX: 49
FD1P3AY: 2
FD1S3AX: 35
FD1S3AY: 1
FD1S3DX: 2
GSR: 1
IB: 7
INV: 8
OB: 10
ORCALUT4: 73
VHI: 1
VLO: 1
Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 51MB peak: 53MB)
Writing Analyst data base D:\cpld\GETPCM~1\GetPcm.srm
@N: MF203 |Set autoconstraint_io
Writing EDIF Netlist and constraint files
@N: MF203 |Set autoconstraint_io
Version 8.8L2
Writing Verilog Simulation files
@N: MF203 |Set autoconstraint_io
Writing VHDL Simulation files
@N: MF203 |Set autoconstraint_io
@N: MF203 |Set autoconstraint_io
Mapper successful!
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Fri Jun 20 12:38:53 2008
###########################################################]
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