getpcmdata_twr.html

PCM数据采集

 Physical Path Details:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383    R21C43C.CLK to     R21C43C.Q0 SLICE_44 (from GetDataPC)
ROUTE         3     1.442     R21C43C.Q0 to     R22C45D.C1 Slot_2
CTOF_DEL    ---     0.260     R22C45D.C1 to     R22C45D.F1 SLICE_125
ROUTE         1     0.528     R22C45D.F1 to     R22C45D.D0 g2
CTOF_DEL    ---     0.260     R22C45D.D0 to     R22C45D.F0 SLICE_125
ROUTE         1     1.199     R22C45D.F0 to     R21C45B.A0 g2_1
CTOF_DEL    ---     0.260     R21C45B.A0 to     R21C45B.F0 SLICE_150
ROUTE         1     1.231     R21C45B.F0 to     R22C46B.A1 U5_un17_count_0_N_14_i
C1TOFCO_DE  ---     0.475     R22C46B.A1 to    R22C46B.FCO U5/SLICE_2
ROUTE         1     0.000    R22C46B.FCO to    R22C46C.FCI U5/data_tmp_2
FCITOF1_DE  ---     0.393    R22C46C.FCI to     R22C46C.F1 U5/SLICE_1
ROUTE         3     1.050     R22C46C.F1 to     R21C46C.B1 U5/I_28_0_S1
CTOF_DEL    ---     0.260     R21C46C.B1 to     R21C46C.F1 U5/SLICE_62
ROUTE         4     2.791     R21C46C.F1 to     R23C26C.CE U5/un13_count (to PCM_CLK_c)
                  --------
                   10.532   (21.8% logic, 78.2% route), 7 logic levels.

 Clock Skew Details:

 Source Clock Path: 

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.674         52.PAD to       52.PADDI Clock
ROUTE         6     4.056       52.PADDI to    R28C46B.CLK Clock_c
REG_DEL     ---     0.383    R28C46B.CLK to     R28C46B.Q0 U3/SLICE_29
ROUTE        17     2.406     R28C46B.Q0 to     R24C2B.CLK CLK_RXD
REG_DEL     ---     0.383     R24C2B.CLK to      R24C2B.Q0 u4/SLICE_37
ROUTE         6     2.227      R24C2B.Q0 to    R21C43C.CLK GetDataPC
                  --------
                   10.129   (14.2% logic, 85.8% route), 3 logic levels.

 Destination Clock Path: 

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.674        197.PAD to      197.PADDI PCM_CLK
ROUTE        17     2.940      197.PADDI to    R23C26C.CLK PCM_CLK_c
                  --------
                    3.614   (18.6% logic, 81.4% route), 1 logic levels.

Report:   92.799MHz is the maximum frequency for this preference.


================================================================================
<A name="par_twr_pref3"></A>Preference: FREQUENCY PORT "Clock" 32.768000 MHz HOLD_MARGIN 3.000000 nS ;
            253 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
WARNING - trce: Clock skew between net 'WrClock' and net
          'RdClock_inferred_clock' not computed: nets may not be related.
          Please refer to preference CLKSKEWDIFF to define external clock
          skew between clock ports. 
--------------------------------------------------------------------------------


Passed:  The following path meets requirements by 21.172ns
         and meets 8544.963ns delay constraint requirement for source clock "CLK_TXD" by 8535.618ns

 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)

   Source:         FF         Q              u2/SendComp  (from CLK_TXD +)
   Destination:    FF         Unknown        RdClock  (to Clock_c +)

   Delay:               3.946ns  (16.3% logic, 83.7% route), 2 logic levels.

 Constraint Details:

       3.946ns physical path delay u2/SLICE_64 to SLICE_42 meets
      30.517ns delay constraint less
       5.399ns skew and 
       0.000ns LSRREC_SET requirement (totaling 25.118ns) by 21.172ns

 Physical Path Details:

   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.383    R23C25C.CLK to     R23C25C.Q0 u2/SLICE_64 (from CLK_TXD)
ROUTE         5     1.199     R23C25C.Q0 to     R22C24A.A0 UartBusy
CTOF_DEL    ---     0.260     R22C24A.A0 to     R22C24A.F0 SLICE_153
ROUTE         1     2.104     R22C24A.F0 to     R22C2B.LSR N_1_i (to Clock_c)
                  --------
                    3.946   (16.3% logic, 83.7% route), 2 logic levels.

 Clock Skew Details:

 Source Clock Path: 

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.674         52.PAD to       52.PADDI Clock
ROUTE         6     4.056       52.PADDI to    R28C46B.CLK Clock_c
REG_DEL     ---     0.383    R28C46B.CLK to     R28C46B.Q0 U3/SLICE_29
ROUTE        17     2.406     R28C46B.Q0 to    R49C29A.CLK CLK_RXD
REG_DEL     ---     0.383    R49C29A.CLK to     R49C29A.Q0 U3/SLICE_30
ROUTE        11     2.227     R49C29A.Q0 to    R23C25C.CLK CLK_TXD
                  --------
                   10.129   (14.2% logic, 85.8% route), 3 logic levels.

 Destination Clock Path: 

   Name    Fanout   Delay (ns)          Site               Resource
PADI_DEL    ---     0.674         52.PAD to       52.PADDI Clock
ROUTE         6     4.056       52.PADDI to     R22C2B.CLK Clock_c
                  --------
                    4.730   (14.2% logic, 85.8% route), 1 logic levels.

Report:  107.009MHz is the maximum frequency for this preference.

<A name="par_twr_rs"></A><B><U><big>Report Summary</big></U></B>
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "CLK_TXD" 0.117028 MHz ;  |    0.117 MHz|  123.320 MHz|     4
                                        |             |             |
FREQUENCY NET "CLK_RXD" 0.468114 MHz ;  |    0.468 MHz|  148.412 MHz|     3
                                        |             |             |
FREQUENCY PORT "PCM_CLK" 8.192000 MHz ; |    8.192 MHz|   92.799 MHz|     7
                                        |             |             |
FREQUENCY PORT "Clock" 32.768000 MHz    |             |             |
HOLD_MARGIN 3.000000 nS ;               |   32.768 MHz|  107.009 MHz|     2
                                        |             |             |
----------------------------------------------------------------------------


All preferences were met.


<A name="par_twr_ts"></A><B><U><big>Timing summary:</big></U></B>

Timing errors: 0  Score: 0
Cumulative negative slack: 0

Constraints cover 1287 paths, 9 nets, and 914 connections (94.9% coverage)

--------------------------------------------------------------------------------




Generated from the file 'D:\CPLD\FPGA\GetPcm\getpcmdata.twr'
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