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<HEAD><TITLE>Place & Route TRACE Report</TITLE>
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<A name="Par_Twr"></A>--------------------------------------------------------------------------------
Lattice TRACE Report, Version ispLever_v70_SP2_Build (24)
Wed Jun 18 20:49:59 2008
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -o checkpnt.twr getpcmdata.ncd getpcmdata.prf
Design file: getpcmdata.ncd
Preference file: getpcmdata.prf
Device,speed: LFXP2-17E,5
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
<A name="par_twr_ps"></A><B><U><big>Preference Summary</big></U></B>
<LI><A href='#par_twr_pref0' Target='right'>FREQUENCY NET "CLK_TXD" 0.117028 MHz (0 errors)</A></LI>
131 items scored, 0 timing errors detected.
Report: 123.320MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref1' Target='right'>FREQUENCY NET "CLK_RXD" 0.468114 MHz (0 errors)</A></LI>
124 items scored, 0 timing errors detected.
Report: 148.412MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref2' Target='right'>FREQUENCY PORT "PCM_CLK" 8.192000 MHz (0 errors)</A></LI>
779 items scored, 0 timing errors detected.
Report: 92.799MHz is the maximum frequency for this preference.
<LI><A href='#par_twr_pref3' Target='right'>FREQUENCY PORT "Clock" 32.768000 MHz HOLD_MARGIN 3.000000 nS (0 errors)</A></LI>
253 items scored, 0 timing errors detected.
Report: 107.009MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
<A name="par_twr_pref0"></A>Preference: FREQUENCY NET "CLK_TXD" 0.117028 MHz ;
131 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 8536.854ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u2/SendComp (from CLK_TXD +)
Destination: FF Unknown u2_UartOutio (to CLK_TXD +)
Delay: 7.416ns (15.7% logic, 84.3% route), 4 logic levels.
Constraint Details:
7.416ns physical path delay u2/SLICE_64 to Uart_Out_MGIOL meets
8544.963ns delay constraint less
0.592ns skew and
0.101ns ONEG0_SET requirement (totaling 8544.270ns) by 8536.854ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.383 R23C25C.CLK to R23C25C.Q0 u2/SLICE_64 (from CLK_TXD)
ROUTE 5 0.949 R23C25C.Q0 to R23C24B.A1 UartBusy
CTOF_DEL --- 0.260 R23C24B.A1 to R23C24B.F1 u2/SLICE_132
ROUTE 16 0.848 R23C24B.F1 to R24C24C.A1 u2/un3_latch
CTOF_DEL --- 0.260 R24C24C.A1 to R24C24C.F1 u2/SLICE_124
ROUTE 1 0.699 R24C24C.F1 to R24C24C.B0 u2/un1_latch_1
CTOF_DEL --- 0.260 R24C24C.B0 to R24C24C.F0 u2/SLICE_124
ROUTE 1 3.757 R24C24C.F0 to IOL_B4A.ONEG0 u2_UartOut_3 (to CLK_TXD)
--------
7.416 (15.7% logic, 84.3% route), 4 logic levels.
Clock Skew Details:
Source Clock:
Delay Connection
2.227ns R49C29A.Q0 to R23C25C.CLK
Destination Clock :
Delay Connection
1.635ns R49C29A.Q0 to IOL_B4A.ECLKO
Report: 123.320MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref1"></A>Preference: FREQUENCY NET "CLK_RXD" 0.468114 MHz ;
124 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
WARNING - trce: Clock skew between net 'Uart_In_c' and net 'CLK_RXD' not
computed: nets may not be related. Please refer to preference
CLKSKEWDIFF to define external clock skew between clock ports.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2129.493ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u4/Start (from Uart_In_c -)
Destination: FF Clock Enable u4/DataRec_1 (to CLK_RXD +)
FF u4/DataRec_0
Delay: 6.494ns (13.9% logic, 86.1% route), 3 logic levels.
Constraint Details:
6.494ns physical path delay SLICE_113 to u4/SLICE_32 meets
2136.231ns delay constraint less
0.244ns CE_SET requirement (totaling 2135.987ns) by 2129.493ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.383 R26C6A.CLK to R26C6A.Q0 SLICE_113 (from Uart_In_c)
ROUTE 12 1.232 R26C6A.Q0 to R26C12B.C0 u4/Start
CTOF_DEL --- 0.260 R26C12B.C0 to R26C12B.F0 u4/SLICE_129
ROUTE 3 0.832 R26C12B.F0 to R26C11B.C0 u4/rstate_3_1
CTOF_DEL --- 0.260 R26C11B.C0 to R26C11B.F0 u4/SLICE_131
ROUTE 5 3.527 R26C11B.F0 to R22C43C.CE u4/un13_rstate (to CLK_RXD)
--------
6.494 (13.9% logic, 86.1% route), 3 logic levels.
Clock Skew Details:
Source Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.674 54.PAD to 54.PADDI Uart_In
ROUTE 2 2.686 54.PADDI to R26C6A.CLK Uart_In_c
--------
3.360 (20.1% logic, 79.9% route), 1 logic levels.
Destination Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.674 52.PAD to 52.PADDI Clock
ROUTE 6 4.056 52.PADDI to R28C46B.CLK Clock_c
REG_DEL --- 0.383 R28C46B.CLK to R28C46B.Q0 U3/SLICE_29
ROUTE 17 2.406 R28C46B.Q0 to R22C43C.CLK CLK_RXD
--------
7.519 (14.1% logic, 85.9% route), 2 logic levels.
Report: 148.412MHz is the maximum frequency for this preference.
================================================================================
<A name="par_twr_pref2"></A>Preference: FREQUENCY PORT "PCM_CLK" 8.192000 MHz ;
779 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
WARNING - trce: Clock skew between net 'GetDataPC' and net 'PCM_CLK_c' not
computed: nets may not be related. Please refer to preference
CLKSKEWDIFF to define external clock skew between clock ports.
WARNING - trce: Clock skew between net 'RdClock_inferred_clock' and net
'WrClock' not computed: nets may not be related. Please refer to
preference CLKSKEWDIFF to define external clock skew between clock
ports.
WARNING - trce: Clock skew between net 'GetDataPC' and net 'WrClock' not
computed: nets may not be related. Please refer to preference
CLKSKEWDIFF to define external clock skew between clock ports.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 111.294ns
and meets 30.517ns delay constraint requirement for source clock "GetDataPC" by 19.741ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q Slot_2 (from GetDataPC +)
Destination: FF Clock Enable U5/PCM_Data_1 (to PCM_CLK_c -)
FF U5/PCM_Data_0
Delay: 10.532ns (21.8% logic, 78.2% route), 7 logic levels.
Constraint Details:
10.532ns physical path delay SLICE_44 to U5/SLICE_38 meets
122.070ns delay constraint less
0.244ns CE_SET requirement (totaling 121.826ns) by 111.294ns
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