getpcmdata_mrp.html

PCM数据采集

u4/SLICE_33 (PFU) covers blocks: u4/DataRec_2, u4/DataRec_3
u4/SLICE_34 (PFU) covers blocks: u4/DataRec_4, u4/DataRec_5
u4/SLICE_35 (PFU) covers blocks: u4/DataRec_6, u4/DataRec_7
u4/SLICE_36 (PFU) covers blocks: u4/DataRec_8
u4/SLICE_37 (PFU) covers blocks: u4/Start_i, u4/GetData
U5/SLICE_38 (PFU) covers blocks: U5/databuf_2_0_0, U5/databuf_2_0_1,
     U5/PCM_Data_0, U5/PCM_Data_1
U5/SLICE_39 (PFU) covers blocks: U5/databuf_2_0_2, U5/databuf_2_0_3,
     U5/PCM_Data_2, U5/PCM_Data_3
U5/SLICE_40 (PFU) covers blocks: U5/databuf_2_0_4, U5/databuf_2_0_5,
     U5/PCM_Data_4, U5/PCM_Data_5
U5/SLICE_41 (PFU) covers blocks: U5/databuf_2_0_6, U5/databuf_2_0_7,
     U5/PCM_Data_6, U5/PCM_Data_7
SLICE_42 (PFU) covers blocks: RdClock_fb, RdClock
SLICE_43 (PFU) covers blocks: Slot_0, Slot_1
SLICE_44 (PFU) covers blocks: Slot_2, Slot_3
SLICE_45 (PFU) covers blocks: Slot_4, Slot_5
SLICE_46 (PFU) covers blocks: Slot_6, Slot_7
U3/SLICE_47 (PFU) covers blocks: U3/Get_CLK_TXD_count_i_0,
     U3/Get_CLK_TXD_count_0
U3/SLICE_48 (PFU) covers blocks: U3/count_3_1, U3/un8_count_axbxc2,
     U3/Get_CLK_RXD_count_1, U3/Get_CLK_RXD_count_2
U3/SLICE_49 (PFU) covers blocks: U3/un8_count_axbxc3, U3/un8_count_axbxc4,
     U3/Get_CLK_RXD_count_3, U3/Get_CLK_RXD_count_4
U3/SLICE_50 (PFU) covers blocks: U3/count_3_5, U3/un8_count_p4,
     U3/Get_CLK_RXD_count_5
U3/SLICE_51 (PFU) covers blocks: U3/count_3_0, U3/Get_CLK_RXD_count_0
U5/SLICE_52 (PFU) covers blocks: U5/chunnel_3_axbxc0, U5/chunnel_3_axbxc1,
     U5/chunnel_0, U5/chunnel_1
U5/SLICE_53 (PFU) covers blocks: U5/chunnel_3_axbxc2, U5/chunnel_3_axbxc3,
     U5/chunnel_2, U5/chunnel_3
U5/SLICE_54 (PFU) covers blocks: U5/chunnel_3_axbxc4, U5/chunnel_3_axbxc6,
     U5/chunnel_4, U5/chunnel_6
U5/SLICE_55 (PFU) covers blocks: U5/chunnel_3_axbxc7, U5/chunnel_3_p7,
     U5/chunnel_7
SLICE_56 (PFU) covers blocks: S_Data_0, U5/databuf_0, U5/databuf_1
U5/SLICE_57 (PFU) covers blocks: U5/databuf_2, U5/databuf_3
U5/SLICE_58 (PFU) covers blocks: U5/databuf_4, U5/databuf_5
U5/SLICE_59 (PFU) covers blocks: U5/databuf_6, U5/databuf_7
SLICE_60 (PFU) covers blocks: U5/chunnel_3_axbxc5, g0_4, U5/chunnel_5
U5/SLICE_61 (PFU) covers blocks: U5/count_3_0, U5/count_3_1, U5/count_0,
     U5/count_1
U5/SLICE_62 (PFU) covers blocks: U5/count_3_2, U5/un13_count, U5/count_2
u2/SLICE_64 (PFU) covers blocks: u2/un3_latch_i, u2/SendComp
u1/SLICE_65 (PFU) covers blocks: u1/XOR2_t8, u1/XOR2_t7, u1/FF_61, u1/FF_60
u1/SLICE_66 (PFU) covers blocks: u1/XOR2_t6, u1/XOR2_t5, u1/FF_59, u1/FF_58
u1/SLICE_67 (PFU) covers blocks: u1/XOR2_t4, u1/XOR2_t3, u1/FF_57, u1/FF_56
u1/SLICE_68 (PFU) covers blocks: u1/XOR2_t2, u1/XOR2_t1, u1/FF_55, u1/FF_54
u1/SLICE_69 (PFU) covers blocks: u1/XOR2_t0, u1/FF_53, u1/FF_52
u1/SLICE_70 (PFU) covers blocks: u1/FF_31, u1/FF_30
u1/SLICE_71 (PFU) covers blocks: u1/FF_29, u1/FF_28
u1/SLICE_72 (PFU) covers blocks: u1/FF_27, u1/FF_26
u1/SLICE_73 (PFU) covers blocks: u1/FF_25, u1/FF_24
u1/SLICE_74 (PFU) covers blocks: u1/FF_23, u1/FF_22
u1/SLICE_75 (PFU) covers blocks: u1/FF_11, u1/FF_10
u1/SLICE_76 (PFU) covers blocks: u1/FF_9, u1/FF_8
u1/SLICE_77 (PFU) covers blocks: u1/FF_7, u1/FF_6
u1/SLICE_78 (PFU) covers blocks: u1/FF_5, u1/FF_4
u1/SLICE_79 (PFU) covers blocks: u1/FF_3, u1/FF_2
u1/SLICE_80 (PFU) covers blocks: u1/FF_51, u1/FF_50
u1/SLICE_81 (PFU) covers blocks: u1/FF_49, u1/FF_48
u1/SLICE_82 (PFU) covers blocks: u1/FF_47, u1/FF_46
u1/SLICE_83 (PFU) covers blocks: u1/FF_45, u1/FF_44
u1/SLICE_84 (PFU) covers blocks: u1/FF_43, u1/FF_42
u1/SLICE_85 (PFU) covers blocks: u1/XOR2_t17, u1/XOR2_t16, u1/FF_91, u1/FF_90
u1/SLICE_86 (PFU) covers blocks: u1/XOR2_t15, u1/XOR2_t14, u1/FF_89, u1/FF_88
u1/SLICE_87 (PFU) covers blocks: u1/XOR2_t13, u1/XOR2_t12, u1/FF_87, u1/FF_86
u1/SLICE_88 (PFU) covers blocks: u1/XOR2_t11, u1/XOR2_t10, u1/FF_85, u1/FF_84
u1/SLICE_89 (PFU) covers blocks: u1/XOR2_t9, u1/FF_83, u1/FF_82
u1/SLICE_90 (PFU) covers blocks: u1/FF_41, u1/FF_40
u1/SLICE_91 (PFU) covers blocks: u1/FF_39, u1/FF_38
u1/SLICE_92 (PFU) covers blocks: u1/FF_37, u1/FF_36
u1/SLICE_93 (PFU) covers blocks: u1/FF_35, u1/FF_34
u1/SLICE_94 (PFU) covers blocks: u1/FF_33, u1/FF_32
u1/SLICE_95 (PFU) covers blocks: u1/FF_21, u1/FF_20
u1/SLICE_96 (PFU) covers blocks: u1/FF_19, u1/FF_18
u1/SLICE_97 (PFU) covers blocks: u1/FF_17, u1/FF_16
u1/SLICE_98 (PFU) covers blocks: u1/FF_15, u1/FF_14
u1/SLICE_99 (PFU) covers blocks: u1/FF_13, u1/FF_12
u1/SLICE_100 (PFU) covers blocks: u1/FF_81, u1/FF_80
u1/SLICE_101 (PFU) covers blocks: u1/FF_79, u1/FF_78
u1/SLICE_102 (PFU) covers blocks: u1/FF_77, u1/FF_76
u1/SLICE_103 (PFU) covers blocks: u1/FF_75, u1/FF_74
u1/SLICE_104 (PFU) covers blocks: u1/FF_73, u1/FF_72
u2/SLICE_106 (PFU) covers blocks: u2/sendbuffer_4_0_0, u2/sendbuffer_4_0_1,
     u2/sendbuffer_0, u2/sendbuffer_1
u2/SLICE_107 (PFU) covers blocks: u2/sendbuffer_4_0_2, u2/sendbuffer_4_0_3,
     u2/sendbuffer_2, u2/sendbuffer_3
u2/SLICE_108 (PFU) covers blocks: u2/sendbuffer_4_0_4, u2/sendbuffer_4_0_5,
     u2/sendbuffer_4, u2/sendbuffer_5
u2/SLICE_109 (PFU) covers blocks: u2/sendbuffer_4_0_6, u2/sendbuffer_4_0_7,
     u2/sendbuffer_6, u2/sendbuffer_7
u2/SLICE_110 (PFU) covers blocks: u2/N_29_i, u2/sendbuffer_8
u2/SLICE_111 (PFU) covers blocks: u2/N_6_i, u2/tstate_n1, u2/tstate_0,
     u2/tstate_1
u2/SLICE_112 (PFU) covers blocks: u2/tstate_n2, u2/tstate_n3, u2/tstate_2,
     u2/tstate_3
SLICE_113 (PFU) covers blocks: u4/Start
u4/SLICE_114 (PFU) covers blocks: u4/recbuffer_0, u4/recbuffer_1
u4/SLICE_115 (PFU) covers blocks: u4/recbuffer_2, u4/recbuffer_3
u4/SLICE_116 (PFU) covers blocks: u4/recbuffer_4, u4/recbuffer_5
u4/SLICE_117 (PFU) covers blocks: u4/recbuffer_6, u4/recbuffer_7
u4/SLICE_118 (PFU) covers blocks: u4/recbuffer_8
u4/SLICE_119 (PFU) covers blocks: u4/rstate_5_0, u4/un23_rstate_axbxc1,
     u4/rstate_3_0, u4/rstate_0, u4/rstate_1
u4/SLICE_120 (PFU) covers blocks: u4/un23_rstate_axbxc2, u4/rstate_3_0,
     u4/un23_rstate_axbxc3, u4/rstate_2, u4/rstate_3
u4/SLICE_121 (PFU) covers blocks: u4/un23_rstate_axbxc4, u4/un23_rstate_axbxc5,
     u4/rstate_4, u4/rstate_5
SLICE_122 (PFU) covers blocks: g0_5, g0_0_0
U3/SLICE_123 (PFU) covers blocks: U3/Get_CLK_RXD_un4_count,
     U3/Get_CLK_RXD_un4_count_1
u2/SLICE_124 (PFU) covers blocks: u2/UartOut_3_f0, u2/un1_latch_1
SLICE_125 (PFU) covers blocks: g2_1, g2
U5/SLICE_126 (PFU) covers blocks: U5/chunnel_3_p4, U5/chunnel_1_2
U5/SLICE_127 (PFU) covers blocks: U5/L_Data_1_sqmuxa_i, U5/L_Data_1_sqmuxa_i_1
SLICE_128 (PFU) covers blocks: g0, g0_3
u4/SLICE_129 (PFU) covers blocks: u4/rstate_3_1, u4/un23_rstate_p4
u4/SLICE_130 (PFU) covers blocks: u4/N_23_i, u4/un18_rstate_1
u4/SLICE_131 (PFU) covers blocks: u4/un13_rstate, u4/un13_rstate_0
u2/SLICE_132 (PFU) covers blocks: u2/sendbuffer10_i, u2/un3_latch, u2/lastlatch
u1/SLICE_133 (PFU) covers blocks: u1/LUT4_23, u1/LUT4_17
u1/SLICE_134 (PFU) covers blocks: u1/LUT4_14, u1/LUT4_22
u1/SLICE_135 (PFU) covers blocks: u1/LUT4_12, u1/LUT4_6
u1/SLICE_136 (PFU) covers blocks: u1/LUT4_13, u1/LUT4_7
u1/SLICE_137 (PFU) covers blocks: u1/LUT4_10, u1/LUT4_8
u1/SLICE_138 (PFU) covers blocks: u1/LUT4_11, u1/LUT4_9
u1/SLICE_139 (PFU) covers blocks: u1/LUT4_20, u1/LUT4_18
u1/SLICE_140 (PFU) covers blocks: u1/LUT4_21, u1/LUT4_19
U5/SLICE_141 (PFU) covers blocks: U5/un17_count_0_I_5_0, U5/chunnel_1_1
U5/SLICE_142 (PFU) covers blocks: U5/un17_count_0_I_6_0, U5/chunnel_1_0
U5/SLICE_143 (PFU) covers blocks: U5/chunnel_1_3, U5/un17_count_0_I_14_0
U5/SLICE_144 (PFU) covers blocks: U5/chunnel_1_4, U5/un17_count_0_I_24_0
u1/SLICE_145 (PFU) covers blocks: u1/LUT4_0, u1/LUT4_1
u1/SLICE_146 (PFU) covers blocks: u1/LUT4_2, u1/LUT4_3
u1/SLICE_147 (PFU) covers blocks: u1/LUT4_4, u1/LUT4_5
u1/SLICE_148 (PFU) covers blocks: u1/LUT4_16, u1/LUT4_15
u2/SLICE_149 (PFU) covers blocks: u2/N_33_i, u2/tstate_5
SLICE_150 (PFU) covers blocks: g0_i_x2_0, U5/un17_count_0_I_32_0, U5/lastfsync
SLICE_151 (PFU) covers blocks: g0_1, U5/un17_count_a_5_p7
U5/SLICE_152 (PFU) covers blocks: U5/un10_count_a0, U5/un17_count_0_I_33_0
SLICE_153 (PFU) covers blocks: N_1_i
SLICE_154 (PFU) covers blocks: GND_0
SLICE_155 (PFU) covers blocks: VCC_0
U5/SLICE_156 (PFU) covers blocks: U5/un2_fsync_i
U5/SLICE_157 (PFU) covers blocks: U5/un17_count_a_5_c1_0_0
U5/SLICE_158 (PFU) covers blocks: U5/un17_count_0_I_15_0
u4/SLICE_159 (PFU) covers blocks: u4/rstate_3_0
u4/SLICE_160 (PFU) covers blocks: u4/un8_rstate
u4/SLICE_161 (PFU) covers blocks: u4/rstate_3_3
u4/SLICE_162 (PFU) covers blocks: u4/rstate_3_2
u4/SLICE_163 (PFU) covers blocks: u4/un1_rstate_2_1
u1/SLICE_164 (PFU) covers blocks: u1/AND2_t20
u1/SLICE_165 (PFU) covers blocks: u1/AND2_t19
Uart_Out (PIC/PIO) covers blocks: Uart_Out_pad, u2_UartOutio
Reset (PIC/PIO) covers blocks: Reset_pad
PCM_Dout (PIC/PIO) covers blocks: PCM_Dout_pad
PCM_Din (PIC/PIO) covers blocks: PCM_Din_pad
PCM_Fsync (PIC/PIO) covers blocks: PCM_Fsync_pad
PCM_CLK (PIC/PIO) covers blocks: PCM_CLK_pad
Uart_In (PIC/PIO) covers blocks: Uart_In_pad
Clock (PIC/PIO) covers blocks: Clock_pad
GSR_INST (GSR) covers block: GSR_INST
u1/pdp_ram_0_0_0 (PDPW16KB) covers block: u1/pdp_ram_0_0_0


<A name="mrp_sig"></A><B><U><big>Signal Cross Reference</big></U></B>
Signal Uart_Out_c - Driver Comp: Uart_Out_MGIOL:O0
   Load Comps: Uart_Out:I1
Signal Reset_c - Driver Comp: Reset:O0
   Load Comps: SLICE_153:I0, GSR_INST:GSR, u1/pdp_ram_0_0_0:RST
Signal fb - Driver Comp: SLICE_42:O0
   Load Comps: SLICE_42:I12
Signal Clock_c - Driver Comp: Clock:O0
   Load Comps: U3/SLICE_29:I15, SLICE_42:I15, U3/SLICE_48:I15, U3/SLICE_49:I15,
        U3/SLICE_50:I15, U3/SLICE_51:I15
Signal N_1_i - Driver Comp: SLICE_153:O0
   Load Comps: SLICE_42:I16
Signal RdClock_inferred_clock - Driver Comp: SLICE_42:O3
   Load Comps: u1/SLICE_6:I15, u1/SLICE_7:I15, u1/SLICE_8:I15, u1/SLICE_9:I15,
        u1/SLICE_10:I15, u1/SLICE_22:I15, SLICE_42:I0, u2/SLICE_64:I0,
        u1/SLICE_65:I15, u1/SLICE_66:I15, u1/SLICE_67:I15, u1/SLICE_68:I15,
        u1/SLICE_69:I15, u1/SLICE_80:I15, u1/SLICE_81:I15, u1/SLICE_82:I15,
        u1/SLICE_83:I15, u1/SLICE_84:I15, u1/SLICE_90:I15, u1/SLICE_91:I15,
        u1/SLICE_92:I15, u1/SLICE_93:I15, u1/SLICE_94:I15, u1/SLICE_95:I15,
        u1/SLICE_96:I15, u1/SLICE_97:I15, u1/SLICE_98:I15, u1/SLICE_99:I15,
        u2/SLICE_110:I0, u2/SLICE_111:I0, u2/SLICE_132:I6, u2/SLICE_132:I4,
        u1/pdp_ram_0_0_0:CLKR
Signal GetComm_8 - Driver Comp: u4/SLICE_36:O3
   Load Comps: SLICE_31:I4
Signal GetDataPC - Driver Comp: u4/SLICE_37:O3
   Load Comps: SLICE_31:I15, SLICE_43:I15, SLICE_44:I15, SLICE_45:I15,
        SLICE_46:I15, SLICE_113:I16
Signal DioSel - Driver Comp: SLICE_31:O3
   Load Comps: SLICE_56:I0, u1/pdp_ram_0_0_0:DI8
Signal GetComm_7 - Driver Comp: u4/SLICE_35:O4
   Load Comps: SLICE_46:I5
Signal Slot_7 - Driver Comp: SLICE_46:O4
   Load Comps: SLICE_150:I6
Signal u2_UartOut_3 - Driver Comp: u2/SLICE_124:O0
   Load Comps: Uart_Out_MGIOL:I14
Signal CLK_TXD - Driver Comp: U3/SLICE_30:O3
   Load Comps: U3/SLICE_30:I0, u2/SLICE_64:I15, u2/SLICE_106:I15,
        u2/SLICE_107:I15, u2/SLICE_108:I15, u2/SLICE_109:I15, u2/SLICE_110:I15,
        u2/SLICE_111:I15, u2/SLICE_112:I15, u2/SLICE_132:I15, Uart_Out_MGIOL:I8
Signal g2_1 - Driver Comp: SLICE_125:O0
   Load Comps: SLICE_150:I1
Signal Slot_5 - Driver Comp: SLICE_45:O4
   Load Comps: SLICE_150:I0, SLICE_151:I6
Signal U5_chunnel_1_5 - Driver Comp: SLICE_60:O1
   Load Comps: U5/SLICE_55:I6, SLICE_60:I0, SLICE_150:I2
Signal g0_5 - Driver Comp: SLICE_122:O2
   Load Comps: U5/SLICE_0:I7, U5/SLICE_52:I3, U5/SLICE_52:I8, U5/SLICE_53:I0,
        U5/SLICE_126:I0, SLICE_150:I3, U5/SLICE_157:I2
Signal U5_un17_count_0_N_14_i - Driver Comp: SLICE_150:O0
   Load Comps: U5/SLICE_2:I8
Signal GND - Driver Comp: SLICE_154:O0
   Load Comps: U5/SLICE_0:I0, U5/SLICE_1:I6, u1/pdp_ram_0_0_0:ADR3
Signal VCC - Driver Comp: SLICE_155:O0
   Load Comps: U5/SLICE_0:I3, U5/SLICE_1:I9, u1/pdp_ram_0_0_0:BE0,
        u1/pdp_ram_0_0_0:BE1
Signal Slot_0 - Driver Comp: SLICE_43:O3
   Load Comps: U5/SLICE_0:I6, SLICE_125:I0, U5/SLICE_142:I0, SLICE_151:I0,
        U5/SLICE_157:I0
Signal U5/I_5_0 - Driver Comp: U5/SLICE_141:O0
   Load Comps: U5/SLICE_0:I8
Signal U5/I_6_0 - Driver Comp: U5/SLICE_142:O0
   Load Comps: U5/SLICE_0:I9
Signal U5/data_tmp_0 - Driver Comp: U5/SLICE_0:O6
   Load Comps: U5/SLICE_2:I17
Signal U5/chunnel_3_p7 - Driver Comp: U5/SLICE_55:O1
   Load Comps: U5/SLICE_54:I9, U5/SLICE_55:I2
Signal U5/chunnel_6 - Driver Comp: U5/SLICE_54:O4
   Load Comps: U5/SLICE_54:I6, U5/SLICE_55:I0, U5/SLICE_152:I6
Signal U5_lastfsync - Driver Comp: SLICE_150:O3
   Load Comps: U5/SLICE_38:I0, U5/SLICE_38:I6, U5/SLICE_39:I0, U5/SLICE_39:I6,
        U5/SLICE_40:I0, U5/SLICE_40:I6, U5/SLICE_41:I0, U5/SLICE_41:I6,
        U5/SLICE_52:I0, U5/SLICE_53:I6, U5/SLICE_54:I7, SLICE_60:I6,
        U5/SLICE_61:I0, U5/SLICE_61:I6, SLICE_122:I6, U5/SLICE_126:I6,
        U5/SLICE_127:I0, SLICE_128:I0, U5/SLICE_141:I0, U5/SLICE_141:I6,
        U5/SLICE_142:I1, U5/SLICE_142:I6, U5/SLICE_143:I0, U5/SLICE_143:I6,
        U5/SLICE_144:I0, U5/SLICE_144:I6, SLICE_150:I7, U5/SLICE_152:I0,
        U5/SLICE_152:I7, U5/SLICE_156:I0, U5/SLICE_158:I0
Signal PCM_Fsync_c - Driver Comp: PCM_Fsync:O0
   Load Comps: U5/SLICE_38:I1, U5/SLICE_38:I7, U5/SLICE_39:I1, U5/SLICE_39:I7,
        U5/SLICE_40:I1, U5/SLICE_40:I7, U5/SLICE_41:I1, U5/SLICE_41:I7,
        U5/SLICE_52:I1, U5/SLICE_53:I7, U5/SLICE_54:I8, SLICE_60:I7,
        U5/SLICE_61:I1, U5/SLICE_61:I7, SLICE_122:I7, U5/SLICE_126:I7,
        U5/SLICE_127:I1, SLICE_128:I1, U5/SLICE_141:I1, U5/SLICE_141:I7,
        U5/SLICE_142:I2, U5/SLICE_142:I7, U5/SLICE_143:I1, U5/SLICE_143:I7,
        U5/SLICE_144:I1, U5/SLICE_144:I7, SLICE_150:I8, SLICE_150:I4,
        U5/SLICE_152:I1, U5/SLICE_152:I8, U5/SLICE_156:I1, U5/SLICE_158:I1
Signal U5/chunnel_3_6 - Driver Comp: U5/SLICE_54:O1
   Load Comps: U5/SLICE_54:I13
Signal U5/chunnel_3_p4 - Driver Comp: U5/SLICE_126:O0
   Load Comps: U5/SLICE_53:I9, U5/SLICE_54:I0, U5/SLICE_55:I7, SLICE_60:I1
Signal U5/chunnel_3 - Driver Comp: U5/SLICE_53:O4
   Load Comps: U5/SLICE_53:I8, U5/SLICE_143:I2, U5/SLICE_143:I8
Signal U5/chunnel_3_3 - Driver Comp: U5/SLICE_53:O1
   Load Comps: U5/SLICE_53:I13
Signal U5/databuf_0 - Driver Comp: SLICE_56:O3
   Load Comps: U5/SLICE_38:I2, U5/SLICE_38:I8, SLICE_56:I5
Signal S_Data - Driver Comp: SLICE_56:O0
   Load Comps: U5/SLICE_38:I3, SLICE_56:I12
Signal U5/databuf_2_0 - Driver Comp: U5/SLICE_38:O0
   Load Comps: U5/SLICE_38:I12
Signal U5/databuf_7 - Driver Comp: U5/SLICE_59:O4
   Load Comps: U5/SLICE_41:I8
Signal U5/databuf_6 - Driver Comp: U5/SLICE_59:O3
   Load Comps: U5/SLICE_41:I2, U5/SLICE_41:I9, U5/SLICE_59:I5
Signal U5/databuf_2_7 - Driver Comp: U5/SLICE_41:O1