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<A name="Mrp"></A> Lattice Mapping Report File for Design 'GetPcm'
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
Command line: D:\ispTOOLS7_0\ispfpga\bin\nt\map.exe -a LatticeXP2 -p LFXP2-17E
-t PQFP208 -s 5 getpcmdata.ngd -o getpcmdata_map.ncd -mp getpcmdata.mrp
getpcmdata.lpf
Target Vendor: LATTICE
Target Device: LFXP2-17EPQFP208
Target Speed: 5
Mapper: mg5a00, version: ispLever_v70_SP2_Build (24)
Mapped on: 06/18/08 20:22:04
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
Number of registers: 192
PFU registers: 191
PIO registers: 1
Number of SLICEs: 164 out of 8280 (2%)
SLICEs(logic/ROM): 164 out of 6795 (2%)
SLICEs(logic/ROM/RAM): 0 out of 1485 (0%)
As RAM: 0 out of 1485 (0%)
As Logic/ROM: 0 out of 1485 (0%)
Number of logic LUT4s: 149
Number of distributed RAM: 0 (0 LUT4s)
Number of ripple logic: 29 (58 LUT4s)
Number of shift registers: 0
Total number of LUT4s: 207
Number of external PIOs: 8 out of 146 (5%)
Number of PIO IDDR/ODDR: 0
Number of PIO FIXEDDELAY: 0
Number of DQSDLLs: 0 out of 2 (0%)
Number of 3-state buffers: 0
Number of PLLs: 0 out of 4 (0%)
Number of block RAMs: 1 out of 15 (7%)
Number of CLKDIVs: 0 out of 2 (0%)
Number of GSRs: 1 out of 1 (100%)
JTAG used : No
Readback used : No
Oscillator used : No
Startup used : No
Notes:-
1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
distributed RAMs) + 2*(Number of ripple logic)
2. Number of logic LUT4s does not include count of distributed RAM and
ripple logic.
DSP Component Details --
------------------------
Number Of Mapped DSP Components:
--------------------------------
MULT36X36B 0
MULT18X18B 0
MULT18X18MACB 0
MULT18X18ADDSUBB 0
MULT18X18ADDSUBSUMB 0
MULT9X9B 0
MULT9X9ADDSUBB 0
MULT9X9ADDSUBSUMB 0
--------------------------------
Number of clocks: 8
Net Clock_c: 6 loads, 6 rising, 0 falling (Driver: PIO Clock )
Net RdClock_inferred_clock: 27 loads, 27 rising, 0 falling (Driver: RdClock
)
Net GetDataPC: 5 loads, 5 rising, 0 falling (Driver: u4/GetData )
Net CLK_TXD: 9 loads, 9 rising, 0 falling (Driver: U3/Get_CLK_TXD_count_1 )
Net WrClock: 27 loads, 27 rising, 0 falling (Driver: U5/L_Data )
Net CLK_RXD: 16 loads, 16 rising, 0 falling (Driver: U3/CLK_RXD )
Net Uart_In_c: 1 loads, 0 rising, 1 falling (Driver: PIO Uart_In )
Net PCM_CLK_c: 17 loads, 0 rising, 17 falling (Driver: PIO PCM_CLK )
Number of Clock Enables: 11
Net U5/N_257_i: 4 loads, 4 LSLICEs
Net U5/un13_count: 4 loads, 4 LSLICEs
Net U5/L_Data_1_sqmuxa_i: 1 loads, 1 LSLICEs
Net u4/un8_rstate: 5 loads, 5 LSLICEs
Net u4/N_23_i: 1 loads, 1 LSLICEs
Net u4/un13_rstate: 5 loads, 5 LSLICEs
Net U3/un4_count: 1 loads, 1 LSLICEs
Net u2/sendbuffer10_i: 1 loads, 1 LSLICEs
Net u2/N_33_i: 7 loads, 7 LSLICEs
Net u1/wren_i: 16 loads, 15 LSLICEs
Net u1/rden_i: 16 loads, 15 LSLICEs
Number of local set/reset merged into GSR: 102
Number of LSRs: 3
Net Reset_c: 1 loads, 0 LSLICEs
Net N_1_i: 1 loads, 1 LSLICEs
Net GetDataPC: 1 loads, 1 LSLICEs
Number of nets driven by tri-state buffers: 0
Top 10 highest fanout non-clock nets:
Net PCM_Fsync_c: 32 loads
Net U5_lastfsync: 31 loads
Net u1/rden_i: 18 loads
Net u1/wren_i: 18 loads
Net u2/un3_latch: 16 loads
Net u4/Start: 12 loads
Net g0_5: 7 loads
Net u2/N_33_i: 7 loads
Net u2/tstate_1: 6 loads
Net u4/rstate_0: 6 loads
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
+---------------------+-----------+-----------+------------+------------+
| IO Name | Direction | Levelmode | IO | FIXEDDELAY |
| | | IO_TYPE | Register | |
+---------------------+-----------+-----------+------------+------------+
| Uart_Out | OUTPUT | LVCMOS25 | OUT | |
+---------------------+-----------+-----------+------------+------------+
| Reset | INPUT | LVCMOS25 | | |
+---------------------+-----------+-----------+------------+------------+
| PCM_Dout | INPUT | LVCMOS25 | | |
+---------------------+-----------+-----------+------------+------------+
| PCM_Din | INPUT | LVCMOS25 | | |
+---------------------+-----------+-----------+------------+------------+
| PCM_Fsync | INPUT | LVCMOS25 | | |
+---------------------+-----------+-----------+------------+------------+
| PCM_CLK | INPUT | LVCMOS25 | | |
+---------------------+-----------+-----------+------------+------------+
| Uart_In | INPUT | LVCMOS25 | | |
+---------------------+-----------+-----------+------------+------------+
| Clock | INPUT | LVCMOS25 | | |
+---------------------+-----------+-----------+------------+------------+
<A name="mrp_mem"></A><B><U><big>Memory Usage</big></U></B>
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation:
The use of the EBR block asynchronous reset requires that certain timing
be met between the clock and the reset within the memory block.
See the device specific data sheet for additional details.
/u1:
EBRs: 1
RAM SLICEs: 0
Logic SLICEs: 80
PFU Registers: 102
-Contains EBR pdp_ram_0_0_0: Width= 9, Depth_R= 512, Depth_W= 512, TYPE=
PDPW16KB, RESETMODE= ASYNC, GSR= ENABLED, MEM_LPC_FILE= FIFO_DC.lpc
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
Signal Uart_In_c_i was merged into signal Uart_In_c
Signal Reset_c_i was merged into signal Reset_c
Signal PCM_CLK_c_i was merged into signal PCM_CLK_c
Signal u1/invout_1 was merged into signal u1/Full
Signal u1/invout_0 was merged into signal Empty
Signal u1/Full_i was merged into signal u1/Full
Signal u1/Empty_i was merged into signal Empty
Signal u1/rRst was merged into signal Reset_c_i
Signal u4/GetDataPC_i was merged into signal GetDataPC
Signal u1/S1_3 undriven or does not drive anything - clipped.
Signal u1/S0_1 undriven or does not drive anything - clipped.
Signal u1/S1_2 undriven or does not drive anything - clipped.
Signal u1/S0_0 undriven or does not drive anything - clipped.
Signal u1/S1_1 undriven or does not drive anything - clipped.
Signal u1/COUT_0 undriven or does not drive anything - clipped.
Signal u1/S1_0 undriven or does not drive anything - clipped.
Signal u1/S0 undriven or does not drive anything - clipped.
Signal u1/S1 undriven or does not drive anything - clipped.
Signal u1/COUT undriven or does not drive anything - clipped.
Signal u1/co4 undriven or does not drive anything - clipped.
Signal u1/co4_1 undriven or does not drive anything - clipped.
Signal u1/S1_4 undriven or does not drive anything - clipped.
Signal u1/S0_2 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO35 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO34 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO33 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO32 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO31 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO30 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO29 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO28 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO27 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO17 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO16 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO15 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO14 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO13 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO12 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO11 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO10 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO9 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO8 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO7 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO6 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO5 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO4 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO3 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO2 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO1 undriven or does not drive anything - clipped.
Signal u1/pdp_ram_0_0_0_DO0 undriven or does not drive anything - clipped.
Signal U5/I_10_0_S1 undriven or does not drive anything - clipped.
Signal U5/I_10_0_S0 undriven or does not drive anything - clipped.
Signal U5/I_28_0_S0 undriven or does not drive anything - clipped.
Signal U5/I_28_0_COUT undriven or does not drive anything - clipped.
Signal U5/I_1_0_S1 undriven or does not drive anything - clipped.
Signal U5/I_1_0_S0 undriven or does not drive anything - clipped.
Block Uart_In_c_i was optimized away.
Block Reset_c_i was optimized away.
Block PCM_CLK_c_i was optimized away.
Block u1/INV_1 was optimized away.
Block u1/INV_0 was optimized away.
Block u1/Full_i was optimized away.
Block u1/Empty_i was optimized away.
Block u1/OR2_t18 was optimized away.
Block u4/GetDataPC_i was optimized away.
<A name="mrp_sym"></A><B><U><big>Symbol Cross Reference</big></U></B>
U5/SLICE_0 (PFU) covers blocks: U5/un17_count_0_I_1_0
U5/SLICE_1 (PFU) covers blocks: U5/L_Data, U5/un17_count_0_I_28_0
U5/SLICE_2 (PFU) covers blocks: U5/un17_count_0_I_10_0
u1/SLICE_3 (PFU) covers blocks: u1/FF_101, u1/FF_100, u1/w_gctr_0
u1/SLICE_4 (PFU) covers blocks: u1/empty_cmp_0
u1/SLICE_5 (PFU) covers blocks: u1/w_gctr_cia
u1/SLICE_6 (PFU) covers blocks: u1/FF_63, u1/FF_62, u1/r_gctr_4
u1/SLICE_7 (PFU) covers blocks: u1/FF_65, u1/FF_64, u1/r_gctr_3
u1/SLICE_8 (PFU) covers blocks: u1/FF_67, u1/FF_66, u1/r_gctr_2
u1/SLICE_9 (PFU) covers blocks: u1/FF_69, u1/FF_68, u1/r_gctr_1
u1/SLICE_10 (PFU) covers blocks: u1/FF_71, u1/FF_70, u1/r_gctr_0
u1/SLICE_11 (PFU) covers blocks: u1/FF_93, u1/FF_92, u1/w_gctr_4
u1/SLICE_12 (PFU) covers blocks: u1/FF_95, u1/FF_94, u1/w_gctr_3
u1/SLICE_13 (PFU) covers blocks: u1/FF_97, u1/FF_96, u1/w_gctr_2
u1/SLICE_14 (PFU) covers blocks: u1/FF_99, u1/FF_98, u1/w_gctr_1
u1/SLICE_15 (PFU) covers blocks: u1/FF_0, u1/a1
u1/SLICE_16 (PFU) covers blocks: u1/full_cmp_4
u1/SLICE_17 (PFU) covers blocks: u1/full_cmp_3
u1/SLICE_18 (PFU) covers blocks: u1/full_cmp_2
u1/SLICE_19 (PFU) covers blocks: u1/full_cmp_1
u1/SLICE_20 (PFU) covers blocks: u1/full_cmp_0
u1/SLICE_21 (PFU) covers blocks: u1/full_cmp_ci_a
u1/SLICE_22 (PFU) covers blocks: u1/FF_1, u1/a0
u1/SLICE_23 (PFU) covers blocks: u1/empty_cmp_4
u1/SLICE_24 (PFU) covers blocks: u1/empty_cmp_3
u1/SLICE_25 (PFU) covers blocks: u1/empty_cmp_2
u1/SLICE_26 (PFU) covers blocks: u1/empty_cmp_1
u1/SLICE_27 (PFU) covers blocks: u1/empty_cmp_ci_a
u1/SLICE_28 (PFU) covers blocks: u1/r_gctr_cia
U3/SLICE_29 (PFU) covers blocks: U3/CLK_RXD_i, U3/CLK_RXD
U3/SLICE_30 (PFU) covers blocks: U3/un2_count_1_SUM1, U3/Get_CLK_TXD_count_1
SLICE_31 (PFU) covers blocks: DioSel
u4/SLICE_32 (PFU) covers blocks: u4/DataRec_0, u4/DataRec_1
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