📄 getpcmdata.tw1
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Lattice TRACE Report, Version ispLever_v70_Prod_Build (55)
Fri Jun 20 12:08:50 2008
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2007 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce -v 1 -gt -o checkpnt.twr getpcmdata_map.ncd getpcmdata.prf
Design file: getpcmdata_map.ncd
Preference file: getpcmdata.prf
Device,speed: LCMXO640C,5
Report level: verbose report, limited to 1 item per preference
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BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "CLK_RXD" 0.468114 MHz ;
123 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 1047.213ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u4/Start (from Uart_In_c -)
Destination: FF Data in u4/rstate_4 (to CLK_RXD +)
Delay: 1.233ns (100.0% logic, 0.0% route), 4 logic levels.
Constraint Details:
1.233ns physical path delay SLICE_54 to u4/SLICE_62 meets
1048.575ns delay constraint less
0.129ns DIN_SET requirement (totaling 1048.446ns) by 1047.213ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.438 SLICE_54.CLK to SLICE_54.Q0 SLICE_54 (from Uart_In_c)
ROUTE 12 e 0.000 SLICE_54.Q0 to SLICE_64.A0 u4/Start
CTOF_DEL --- 0.265 SLICE_64.A0 to SLICE_64.F0 SLICE_64
ROUTE 3 e 0.000 SLICE_64.F0 to SLICE_63.C0 u4/rstate_3_1
CTOF_DEL --- 0.265 SLICE_63.C0 to SLICE_63.F0 SLICE_63
ROUTE 2 e 0.000 SLICE_63.F0 to u4/SLICE_62.C0 u4/un23_rstate_p4
CTOF_DEL --- 0.265 u4/SLICE_62.C0 to u4/SLICE_62.F0 u4/SLICE_62
ROUTE 1 e 0.000 u4/SLICE_62.F0 to 4/SLICE_62.DI0 u4/un23_rstate_axbxc4 (to CLK_RXD)
--------
1.233 (100.0% logic, 0.0% route), 4 logic levels.
Report: 734.214MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "CLK_TXD" 0.117028 MHz ;
79 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 1047.516ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q u2/tstate_1 (from CLK_TXD +)
Destination: FF Data in u2/UartOut (to CLK_TXD +)
Delay: 0.930ns (100.0% logic, 0.0% route), 3 logic levels.
Constraint Details:
0.930ns physical path delay u2/SLICE_52 to u2/SLICE_43 meets
1048.575ns delay constraint less
0.129ns DIN_SET requirement (totaling 1048.446ns) by 1047.516ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.400 2/SLICE_52.CLK to u2/SLICE_52.Q1 u2/SLICE_52 (from CLK_TXD)
ROUTE 6 e 0.000 u2/SLICE_52.Q1 to u2/SLICE_43.A1 u2/tstate_1
CTOF_DEL --- 0.265 u2/SLICE_43.A1 to u2/SLICE_43.F1 u2/SLICE_43
ROUTE 1 e 0.000 u2/SLICE_43.F1 to u2/SLICE_43.C0 u2/un1_tstate_1
CTOF_DEL --- 0.265 u2/SLICE_43.C0 to u2/SLICE_43.F0 u2/SLICE_43
ROUTE 1 e 0.000 u2/SLICE_43.F0 to 2/SLICE_43.DI0 u2/UartOut_2 (to CLK_TXD)
--------
0.930 (100.0% logic, 0.0% route), 3 logic levels.
Report: 944.287MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "PCM_CLK" 8.192000 MHz ;
784 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 118.350ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q U5/chunnel_0 (from PCM_CLK_c -)
Destination: FF Unknown U5/L_Data (to PCM_CLK_c -)
Delay: 3.531ns (100.0% logic, 0.0% route), 9 logic levels.
Constraint Details:
3.531ns physical path delay U5/SLICE_32 to U5/SLICE_44 meets
122.070ns delay constraint less
0.189ns CE_SET requirement (totaling 121.881ns) by 118.350ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.438 5/SLICE_32.CLK to U5/SLICE_32.Q0 U5/SLICE_32 (from PCM_CLK_c)
ROUTE 1 e 0.000 U5/SLICE_32.Q0 to U5/SLICE_6.A0 U5/chunnel_0
A0TOFCO_DE --- 0.630 U5/SLICE_6.A0 to U5/SLICE_6.FCO U5/SLICE_6
ROUTE 1 e 0.000 U5/SLICE_6.FCO to U5/SLICE_5.FCI U5/un1_chunnel_cry_1
FCITOFCO_D --- 0.101 U5/SLICE_5.FCI to U5/SLICE_5.FCO U5/SLICE_5
ROUTE 1 e 0.000 U5/SLICE_5.FCO to U5/SLICE_4.FCI U5/un1_chunnel_cry_3
FCITOFCO_D --- 0.101 U5/SLICE_4.FCI to U5/SLICE_4.FCO U5/SLICE_4
ROUTE 1 e 0.000 U5/SLICE_4.FCO to U5/SLICE_3.FCI U5/un1_chunnel_cry_5
TLATCH_DEL --- 0.919 U5/SLICE_3.FCI to U5/SLICE_3.Q1 U5/SLICE_3
ROUTE 1 e 0.000 U5/SLICE_3.Q1 to U5/SLICE_35.A1 U5/un1_chunnel_cry_6_0_S1
CTOF_DEL --- 0.265 U5/SLICE_35.A1 to U5/SLICE_35.F1 U5/SLICE_35
ROUTE 2 e 0.000 U5/SLICE_35.F1 to SLICE_1.B1 U5/chunnel_3_7
B1TOFCO_DE --- 0.547 SLICE_1.B1 to SLICE_1.FCO SLICE_1
ROUTE 2 e 0.000 SLICE_1.FCO to U5/SLICE_44.D1 U5/data_tmp_3
CTOF_DEL --- 0.265 U5/SLICE_44.D1 to U5/SLICE_44.F1 U5/SLICE_44
ROUTE 5 e 0.000 U5/SLICE_44.F1 to SLICE_66.A0 U5/un12_chunnel
CTOF_DEL --- 0.265 SLICE_66.A0 to SLICE_66.F0 SLICE_66
ROUTE 1 e 0.000 SLICE_66.F0 to U5/SLICE_44.CE U5/L_Data_1_sqmuxa_i (to PCM_CLK_c)
--------
3.531 (100.0% logic, 0.0% route), 9 logic levels.
Report: 268.817MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "Clock" 32.768000 MHz HOLD_MARGIN 3.000000 nS ;
191 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 27.239ns
and meets 122.070ns delay constraint requirement for source clock "PCM_CLK_c" by 118.792ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q U5/chunnel_0 (from PCM_CLK_c -)
Destination: FF Unknown U5/un16_chunnel_0_I_19_0 (to GetDataPC +)
Delay: 2.799ns (100.0% logic, 0.0% route), 5 logic levels.
Constraint Details:
2.799ns physical path delay U5/SLICE_32 to SLICE_1 meets
30.517ns delay constraint less
0.479ns FCI_SET requirement (totaling 30.038ns) by 27.239ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.438 5/SLICE_32.CLK to U5/SLICE_32.Q0 U5/SLICE_32 (from PCM_CLK_c)
ROUTE 1 e 0.000 U5/SLICE_32.Q0 to U5/SLICE_6.A0 U5/chunnel_0
A0TOFCO_DE --- 0.630 U5/SLICE_6.A0 to U5/SLICE_6.FCO U5/SLICE_6
ROUTE 1 e 0.000 U5/SLICE_6.FCO to U5/SLICE_5.FCI U5/un1_chunnel_cry_1
TLATCH_DEL --- 0.919 U5/SLICE_5.FCI to U5/SLICE_5.Q1 U5/SLICE_5
ROUTE 1 e 0.000 U5/SLICE_5.Q1 to U5/SLICE_33.A1 U5/un1_chunnel_cry_2_0_S1
CTOF_DEL --- 0.265 U5/SLICE_33.A1 to U5/SLICE_33.F1 U5/SLICE_33
ROUTE 2 e 0.000 U5/SLICE_33.F1 to SLICE_2.B1 U5/chunnel_3_3
B1TOFCO_DE --- 0.547 SLICE_2.B1 to SLICE_2.FCO SLICE_2
ROUTE 1 e 0.000 SLICE_2.FCO to SLICE_1.FCI U5/data_tmp_1 (to GetDataPC)
--------
2.799 (100.0% logic, 0.0% route), 5 logic levels.
Report: 305.064MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "CLK_RXD" 0.468114 MHz ; | 0.468 MHz| 734.214 MHz| 4
| | |
FREQUENCY NET "CLK_TXD" 0.117028 MHz ; | 0.117 MHz| 944.287 MHz| 3
| | |
FREQUENCY PORT "PCM_CLK" 8.192000 MHz ; | 8.192 MHz| 268.817 MHz| 9
| | |
FREQUENCY PORT "Clock" 32.768000 MHz | | |
HOLD_MARGIN 3.000000 nS ; | 32.768 MHz| 305.064 MHz| 5
| | |
----------------------------------------------------------------------------
All preferences were met.
Timing summary:
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 1177 paths, 8 nets, and 421 connections (91.3% coverage)
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