prev_cmp_led.qmsg

FPGA和VHDL的全过程和源码

{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 09 07:30:04 2008 " "Info: Processing started: Wed Apr 09 07:30:04 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off led -c led " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off led -c led" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "148 " "Info: Allocated 148 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 09 07:30:08 2008 " "Info: Processing ended: Wed Apr 09 07:30:08 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Apr 09 07:30:09 2008 " "Info: Processing started: Wed Apr 09 07:30:09 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off led -c led --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off led -c led --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "myled.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/led/myled.bdf" { { 24 96 264 40 "clk" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\] " "Info: Detected ripple clock \"lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\]\" as buffer" {  } { { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/db/cntr_qeh.tdf" 242 8 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register led:inst\|count\[2\] register led:inst\|q1\[4\] 204.21 MHz 4.897 ns Internal " "Info: Clock \"clk\" has Internal fmax of 204.21 MHz between source register \"led:inst\|count\[2\]\" and destination register \"led:inst\|q1\[4\]\" (period= 4.897 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.636 ns + Longest register register " "Info: + Longest register to register delay is 4.636 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led:inst\|count\[2\] 1 REG LC_X48_Y24_N6 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X48_Y24_N6; Fanout = 10; REG Node = 'led:inst\|count\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led:inst|count[2] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.347 ns) + CELL(0.292 ns) 1.639 ns led:inst\|q1~432 2 COMB LC_X50_Y24_N1 2 " "Info: 2: + IC(1.347 ns) + CELL(0.292 ns) = 1.639 ns; Loc. = LC_X50_Y24_N1; Fanout = 2; COMB Node = 'led:inst\|q1~432'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.639 ns" { led:inst|count[2] led:inst|q1~432 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.090 ns) + CELL(0.442 ns) 3.171 ns led:inst\|Selector3~59 3 COMB LC_X48_Y24_N7 1 " "Info: 3: + IC(1.090 ns) + CELL(0.442 ns) = 3.171 ns; Loc. = LC_X48_Y24_N7; Fanout = 1; COMB Node = 'led:inst\|Selector3~59'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.532 ns" { led:inst|q1~432 led:inst|Selector3~59 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.292 ns) 3.913 ns led:inst\|Selector3~60 4 COMB LC_X48_Y24_N0 1 " "Info: 4: + IC(0.450 ns) + CELL(0.292 ns) = 3.913 ns; Loc. = LC_X48_Y24_N0; Fanout = 1; COMB Node = 'led:inst\|Selector3~60'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.742 ns" { led:inst|Selector3~59 led:inst|Selector3~60 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.414 ns) + CELL(0.309 ns) 4.636 ns led:inst\|q1\[4\] 5 REG LC_X48_Y24_N2 3 " "Info: 5: + IC(0.414 ns) + CELL(0.309 ns) = 4.636 ns; Loc. = LC_X48_Y24_N2; Fanout = 3; REG Node = 'led:inst\|q1\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.723 ns" { led:inst|Selector3~60 led:inst|q1[4] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.335 ns ( 28.80 % ) " "Info: Total cell delay = 1.335 ns ( 28.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.301 ns ( 71.20 % ) " "Info: Total interconnect delay = 3.301 ns ( 71.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.636 ns" { led:inst|count[2] led:inst|q1~432 led:inst|Selector3~59 led:inst|Selector3~60 led:inst|q1[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.636 ns" { led:inst|count[2] {} led:inst|q1~432 {} led:inst|Selector3~59 {} led:inst|Selector3~60 {} led:inst|q1[4] {} } { 0.000ns 1.347ns 1.090ns 0.450ns 0.414ns } { 0.000ns 0.292ns 0.442ns 0.292ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.730 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 7.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/led/myled.bdf" { { 24 96 264 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\] 2 REG LC_X8_Y13_N6 16 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N6; Fanout = 16; REG Node = 'lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.584 ns) + CELL(0.711 ns) 7.730 ns led:inst\|q1\[4\] 3 REG LC_X48_Y24_N2 3 " "Info: 3: + IC(3.584 ns) + CELL(0.711 ns) = 7.730 ns; Loc. = LC_X48_Y24_N2; Fanout = 3; REG Node = 'led:inst\|q1\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.295 ns" { lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|q1[4] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.30 % ) " "Info: Total cell delay = 3.115 ns ( 40.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.615 ns ( 59.70 % ) " "Info: Total interconnect delay = 4.615 ns ( 59.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.730 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|q1[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.730 ns" { clk {} clk~out0 {} lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] {} led:inst|q1[4] {} } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.730 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/led/myled.bdf" { { 24 96 264 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\] 2 REG LC_X8_Y13_N6 16 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N6; Fanout = 16; REG Node = 'lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.584 ns) + CELL(0.711 ns) 7.730 ns led:inst\|count\[2\] 3 REG LC_X48_Y24_N6 10 " "Info: 3: + IC(3.584 ns) + CELL(0.711 ns) = 7.730 ns; Loc. = LC_X48_Y24_N6; Fanout = 10; REG Node = 'led:inst\|count\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.295 ns" { lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|count[2] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.30 % ) " "Info: Total cell delay = 3.115 ns ( 40.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.615 ns ( 59.70 % ) " "Info: Total interconnect delay = 4.615 ns ( 59.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.730 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|count[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.730 ns" { clk {} clk~out0 {} lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] {} led:inst|count[2] {} } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.730 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|q1[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.730 ns" { clk {} clk~out0 {} lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] {} led:inst|q1[4] {} } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.730 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|count[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.730 ns" { clk {} clk~out0 {} lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] {} led:inst|count[2] {} } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.636 ns" { led:inst|count[2] led:inst|q1~432 led:inst|Selector3~59 led:inst|Selector3~60 led:inst|q1[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.636 ns" { led:inst|count[2] {} led:inst|q1~432 {} led:inst|Selector3~59 {} led:inst|Selector3~60 {} led:inst|q1[4] {} } { 0.000ns 1.347ns 1.090ns 0.450ns 0.414ns } { 0.000ns 0.292ns 0.442ns 0.292ns 0.309ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.730 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|q1[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.730 ns" { clk {} clk~out0 {} lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] {} led:inst|q1[4] {} } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.730 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|count[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.730 ns" { clk {} clk~out0 {} lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] {} led:inst|count[2] {} } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "led:inst\|count\[1\] rst clk 3.318 ns register " "Info: tsu for register \"led:inst\|count\[1\]\" (data pin = \"rst\", clock pin = \"clk\") is 3.318 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.011 ns + Longest pin register " "Info: + Longest pin to register delay is 11.011 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns rst 1 PIN PIN_124 13 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_124; Fanout = 13; PIN Node = 'rst'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "myled.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/led/myled.bdf" { { 136 120 288 152 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.515 ns) + CELL(0.590 ns) 9.574 ns led:inst\|count\[0\]~257 2 COMB LC_X49_Y24_N2 3 " "Info: 2: + IC(7.515 ns) + CELL(0.590 ns) = 9.574 ns; Loc. = LC_X49_Y24_N2; Fanout = 3; COMB Node = 'led:inst\|count\[0\]~257'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.105 ns" { rst led:inst|count[0]~257 } "NODE_NAME" } } { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.128 ns) + CELL(0.309 ns) 11.011 ns led:inst\|count\[1\] 3 REG LC_X48_Y24_N1 11 " "Info: 3: + IC(1.128 ns) + CELL(0.309 ns) = 11.011 ns; Loc. = LC_X48_Y24_N1; Fanout = 11; REG Node = 'led:inst\|count\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.437 ns" { led:inst|count[0]~257 led:inst|count[1] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.368 ns ( 21.51 % ) " "Info: Total cell delay = 2.368 ns ( 21.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.643 ns ( 78.49 % ) " "Info: Total interconnect delay = 8.643 ns ( 78.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.011 ns" { rst led:inst|count[0]~257 led:inst|count[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.011 ns" { rst {} rst~out0 {} led:inst|count[0]~257 {} led:inst|count[1] {} } { 0.000ns 0.000ns 7.515ns 1.128ns } { 0.000ns 1.469ns 0.590ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.730 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 7.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/led/myled.bdf" { { 24 96 264 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\] 2 REG LC_X8_Y13_N6 16 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N6; Fanout = 16; REG Node = 'lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.584 ns) + CELL(0.711 ns) 7.730 ns led:inst\|count\[1\] 3 REG LC_X48_Y24_N1 11 " "Info: 3: + IC(3.584 ns) + CELL(0.711 ns) = 7.730 ns; Loc. = LC_X48_Y24_N1; Fanout = 11; REG Node = 'led:inst\|count\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.295 ns" { lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|count[1] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.30 % ) " "Info: Total cell delay = 3.115 ns ( 40.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.615 ns ( 59.70 % ) " "Info: Total interconnect delay = 4.615 ns ( 59.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.730 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|count[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.730 ns" { clk {} clk~out0 {} lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] {} led:inst|count[1] {} } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.011 ns" { rst led:inst|count[0]~257 led:inst|count[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.011 ns" { rst {} rst~out0 {} led:inst|count[0]~257 {} led:inst|count[1] {} } { 0.000ns 0.000ns 7.515ns 1.128ns } { 0.000ns 1.469ns 0.590ns 0.309ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.730 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|count[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.730 ns" { clk {} clk~out0 {} lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] {} led:inst|count[1] {} } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk led\[5\] led:inst\|q1\[5\] 16.111 ns register " "Info: tco from clock \"clk\" to destination pin \"led\[5\]\" through register \"led:inst\|q1\[5\]\" is 16.111 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.730 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "myled.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/led/myled.bdf" { { 24 96 264 40 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.031 ns) + CELL(0.935 ns) 3.435 ns lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\] 2 REG LC_X8_Y13_N6 16 " "Info: 2: + IC(1.031 ns) + CELL(0.935 ns) = 3.435 ns; Loc. = LC_X8_Y13_N6; Fanout = 16; REG Node = 'lpm_counter0:inst1\|lpm_counter:lpm_counter_component\|cntr_qeh:auto_generated\|safe_q\[23\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.966 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] } "NODE_NAME" } } { "db/cntr_qeh.tdf" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/db/cntr_qeh.tdf" 242 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.584 ns) + CELL(0.711 ns) 7.730 ns led:inst\|q1\[5\] 3 REG LC_X50_Y24_N5 4 " "Info: 3: + IC(3.584 ns) + CELL(0.711 ns) = 7.730 ns; Loc. = LC_X50_Y24_N5; Fanout = 4; REG Node = 'led:inst\|q1\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.295 ns" { lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|q1[5] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 40.30 % ) " "Info: Total cell delay = 3.115 ns ( 40.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.615 ns ( 59.70 % ) " "Info: Total interconnect delay = 4.615 ns ( 59.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.730 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|q1[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.730 ns" { clk {} clk~out0 {} lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] {} led:inst|q1[5] {} } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.157 ns + Longest register pin " "Info: + Longest register to pin delay is 8.157 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led:inst\|q1\[5\] 1 REG LC_X50_Y24_N5 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X50_Y24_N5; Fanout = 4; REG Node = 'led:inst\|q1\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { led:inst|q1[5] } "NODE_NAME" } } { "led.vhd" "" { Text "D:/lecture/embed/FPGA/FPGAExample/led/led.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.033 ns) + CELL(2.124 ns) 8.157 ns led\[5\] 2 PIN PIN_15 0 " "Info: 2: + IC(6.033 ns) + CELL(2.124 ns) = 8.157 ns; Loc. = PIN_15; Fanout = 0; PIN Node = 'led\[5\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.157 ns" { led:inst|q1[5] led[5] } "NODE_NAME" } } { "myled.bdf" "" { Schematic "D:/lecture/embed/FPGA/FPGAExample/led/myled.bdf" { { 120 416 592 136 "led\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.124 ns ( 26.04 % ) " "Info: Total cell delay = 2.124 ns ( 26.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.033 ns ( 73.96 % ) " "Info: Total interconnect delay = 6.033 ns ( 73.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.157 ns" { led:inst|q1[5] led[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.157 ns" { led:inst|q1[5] {} led[5] {} } { 0.000ns 6.033ns } { 0.000ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.730 ns" { clk lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] led:inst|q1[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.730 ns" { clk {} clk~out0 {} lpm_counter0:inst1|lpm_counter:lpm_counter_component|cntr_qeh:auto_generated|safe_q[23] {} led:inst|q1[5] {} } { 0.000ns 0.000ns 1.031ns 3.584ns } { 0.000ns 1.469ns 0.935ns 0.711ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.157 ns" { led:inst|q1[5] led[5] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.157 ns" { led:inst|q1[5] {} led[5] {} } { 0.000ns 6.033ns } { 0.000ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "led:inst\|count\[0\] rst clk -3.173 ns register " "Info: th for register \"led:inst\|count\[0\]\" (data pin = \"rst\", clock pin = \"clk\") is -3.173 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.730 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.730 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_28 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 24; CLK Node = 'clk'" {  } { { "c:/altera